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depth-estimation-light-field

:heavy_check_mark:A collection of code of depth estimation using light field data.

depth-from-motion

[ECCV 2022 oral] Monocular 3D Object Detection with Depth from Motion

depth-image-quality-enhancement

depth-image-segmentation

Surface orientation based segmentation of images taken from depth sensing camera

depth-mapper

Generates a depth map from a focal stack of images using OpenCV 📷

depth_clustering

:taxi: Fast and robust clustering of point clouds generated with a Velodyne sensor.

depth_map_upsampling_tof

This is a matlab implementation of J.Park's work "High Quality Depth Map Upsampling for 3D-TOF Cameras" . We test our implementation with a TOF-Simulated.mat file, and our results is close to the original authors.

depthai-core

DepthAI C++ Library

depthai-kicad

depthai-python

DepthAI Python Library

depthai_hand_tracker

Running Google Mediapipe Hand Tracking models on Luxonis DepthAI hardware (OAK-D-lite, OAK-D, OAK-1,...)

depthcam_hector_slam

a fusion of Hector SLAM 2d map construction and depth camera's pointcloud data

depthimage_to_laserscan

Converts a depth image to a laser scan for use with navigation and localization.

depthlocalisation

depthstillation

Demo code for paper "Learning optical flow from still images", CVPR 2021.

depthstream

GPU-accelerated stereo vision algorithm

depthvisualizer

OpenGL Based Python Library for 3D visualization of Point Clouds & Depth Maps

depthy

depth map computation

des-cpa-lab

Implementation of a correlation power analysis attack on a DES crypto device

desfireaes

C code for NXP MIFARE DESFire cards using AES

design-and-verification-of-ddr3-memory-controller

The memory model was leveraged from micron.

design-and-verification-of-ddr3-sdram-memory-controller

Designed a closed page policy memory controller following the timing specifications for DDR3 DRAM in system verilog. Was responsible for setting up the interfaces and writing tasks for various operations. Performed randomized, Constrained, and directed test cases to validate our DUT.

design-and-verification-of-functionality-using-core-generator

Using Core generator Designed and Verified functionality of following blocks i. 5x5 unsigned multiplier ii. 32x4 Simple Dual Port Ram iii. 5 Bit Adder/Subtractor Circuit using Fabric(Verify using FPGA Editor) iv. 3 Bit Adder/Subtractor Circuit using DSP48(Verify using FPGA Editor) v. 8x8 ROM with initial value provided from .coe file

design-blocks

design-esp32

GuruModem Design Files

design-files

MinnowBoard.org Official Hardware Design Files

design-of-buck-converter-based-on-stm32-in-dcm-mode

基于STM32的DCM模式下的BUCK变换器设计

design-of-spread-spectrum-correlator

RTL design of a Spread spectrum correlator using Verilog

design-of-the-best-signal-receivers-

UESTC-信号最佳接收检测的设计与实现

design-verification-of-a-rtl-model-multiport-alu-unit

RTL Design: Pipelined Multi port Calculator with 2 ALUs one for Add/Subtract and other for Shift operations. Developed a Gray box model with on-the fly constraint random simulation generation. Used reference model based scoreboard technique with functional coverage to verify the DUV. Language used: System Verilog