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This project forked from sukrutkelkar/design-verification-of-a-rtl-model-multiport-alu-unit

RTL Design: Pipelined Multi port Calculator with 2 ALUs one for Add/Subtract and other for Shift operations. Developed a Gray box model with on-the fly constraint random simulation generation. Used reference model based scoreboard technique with functional coverage to verify the DUV. Language used: System Verilog