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superh_rev4-sdr-stm32h7-144pin

Ultra performance narrow-band receiver. Most of the important parts are fabbed in the US. The superH is a 480MHz STM32H743 based SDR capable of decoding advanced protocols such as P25 without a host PC.

superhexagonfpga

FPGA clone of the game Super Hexagon

superpixel-benchmark

An extensive evaluation and comparison of 28 state-of-the-art superpixel algorithms on 5 datasets.

superpoint_slam

SuperPoint + ORB_SLAM2

superprobe

A single PCB implementation of Carlson's superprobe in Kicad

superscalar

A Superscalar CPU implementation using RISC-V

superscalar-1

superscalar-2

superscalar-3

A superscalar processor in Python

superscalar-4

superscalar-asci

A ASIC superscalar processor

superscalar-mips

A MIPS dual-issue superscalar processor

superscalar-mips-1

Project aimed at implementing a MIPS version capable of executing 3 simultaneous instructions, while using speculative execution. The processor must use Tomasulo algorithm or Scoreboarding.

superscalar-out-of-order-simulator

superscalar-out-of-order-simulator-1

superscalar-pipelined-machine-simulator

superscalar-processor

Implementation of a superscalar processor that makes use of a simplified Tomasulo's algorithm. Allows for out-of-order execution and ensures dependencies are maintained.

superscalar-processor-1

关于现代超标量处理器设计相关的一些模拟器等

superscalar-processor-using-tomasulo-s-algorithm

In this Research Project an approach to modify the existing Tomasulo’s Algorithm by combining it with Superscalar Instruction Dispatching techniques and to compare the Performance of the proposed design with existing Tomasulo’s Algorithm which issues one instruction per cycle as well as an In-order Processor which consists of a Single ALU Unit and performs issuing and executing of instructions in-order.

superscalar-riscv-cpu

SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.

superscalar_architecture

superscalar_instruction_dispatch_unit

a Superscalar Instruction Dispatch Unit using Tomasulo’s algorithm

superscalar_pipeline_processor

Design consists of a 32-bit MIPS superscalar pipeline processor in functional Verilog. Runs a cache based memory system, a branch predictor, and a 2-way superscalar pipeline processor issuing two instructions at a time. Intended for creators Yiming Gan and Dylan Vanmali.

superscalar_processor

superscalar_processor-1

superscalar_risc-v

superscalar_risc_processor

superscalar_verilog

An implementation of super scalar processor for MIPS ISA in Verilog.

superscalarprocessor

Semester 6 Advanced Processor Design Project 1

supersdr

SuperSDR: multiplatform KiwiSDR + CAT transceiver integrator