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cfm

A 16-bit CPU and self-hosting Forth system for the Lattice ICE40 FPGA, written in Haskell.

cfront-3

self education and historical research of the C++ compiler cfront v3

cftp

Configurable Fault Tolerant Processor

cfu

RISC-V FPGA SIG Custom Function Unit Specification

cfu-playground

Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM).

cgal

The public CGAL repository, see the README below

cgc-monitor

Cyber Grand Challenge forensics harness and automated analysis based on Simics

cgen

The development tree for CGEN for the Synopsys DesignWare ARC processor family

cggtts

:satellite: :artificial_satellite: CGGTTS data for Two Way Satellite Time Transfer

cglib

cglib - Byte Code Generation Library is high level API to generate and transform Java byte code. It is used by AOP, testing, data access frameworks to generate dynamic proxy objects and intercept field access.

cgmm-mvdr

Implementation of the CGMM-MVDR beamforming

cgmpcx1006-cyusb3014

Amplifier Board PCB Project

cgra-gnss

cgra-me

this is not mine. just using this to read the code online.

cgra-routing

SForum 2020 : "A Run-time Hardware Routing Implementation for CGRA Overlays" code and data.

cgra-systemc

SystemC implementation of a parameterizable CGRA

cgra_coreir

CGRA design converted to CoreIR

cgra_mapping

CGRA_Mapping

cgra_pnr

Fast PnR toolchain for CGRA

cgra_pnr_build

cgra_verilog_mirror

Mirror of CGRA verilog generation on kiwi

cgraflow

Integration test for entire CGRA flow

cgraflowdoc

Documentation for the entire CGRAFlow

cgragenerator

cgragenerator-1

cgramapper

CoreIR based mapping tool for CGRA

cgramapping

cgraverification

The current test and formal verification status for the CGRA.

ch32v103

L2 R2：WCH RISC-V MCU(CH32V103)

ch552-ag1k-msd

Load bitstream to AG1K series FPGA using CH552