vlsida / openram Goto Github PK

when i run this config file

num_words = 16  
tech_name = "scn4m_subm"  
nominal_corner_only = True  
netlist_only = False  
route_supplies = True  
check_lvsdrc = True  
inline_lvsdrc = True  
analytical_delay = False  
output_path = "temp"  
output_name = "sram_{0}_{1}_{2}".format(word_size,  
                                        num_words,  
                                        tech_name)

i get LVS mismatch error for pnand2_0. ihave attached the log file
sram_2_16_scn4m_subm.log

I will just describe an example. The code for RISC-V CPU with the compressed instruction extension is a mix of 32 and 16 bit instructions, this meas 32bit instructions are not always 32bit aligned.

If the CPU requests an unaligned 32bit instruction, two memory read cycles must be performed to fetch it. A buffer containing the previous read can be used to avoid repeating the read, but this it does not help if a branch is taken.

A RAM/ROM with a 32bit data bus and addressing granularity of 16bit would enable CPU instruction fetches without overhead. There are use cases where reading only 16bit data would be needed (if in the previous cycle 32bits were read containing a 16bit instruction and half of a 32bit instruction).

The same functionality can be achieved with a pair of memories with 16bit data buses and some extra logic. But a dedicated solution could probably offer better power optimizations.

Open questions are:

• how to handle the end of the array (would it wrap),
• how to combine multiple memories,
• little/big endian,
• are there enough area and speed improvements to make it worth?

Hi,
I'm working to generate some rams for use in the OpenROAD project and running into some issues. Using the provided compiler/tests/config_freepdk45.py tests, the generated lef has SIZE 14.005 BY 38.2 however it has pin port rectangles outside of the macro area. For example

         LAYER metal3 ;
         RECT  -10.32 37.24 13.6 37.38 ;

Here's an image of what it looks like

I was able to workaround this by changing the lef to accommodate the full area and then shift the origin

  SIZE 24.325 BY 47.7 ;
   ORIGIN 10.32 9.5 ;

I am able to generate 32x32, 256x256, 16x2, etc array successfully but it gives the error while generating 16x16 array.
ERROR: file calibre.py: line 218: control_logic_rw Geometries: 7526 Checks: 167 Errors: 1
/home/gyanendra/openram/compiler/debug.py(46)error()
assert return_value == 0

Can you please help me in resolving the issue.

Thanks in advance.

The clock pin capacitance is wrong in the lib files. It seems to be a single DFF, but it should be larger since it has multiple fanouts.

Add the clock buffer internal to control logic. Simulation uses
1-4-8-16 inverters right now. Replace simulation with simple clock
buffer after fixing.

Can anyone resolve these three queries?

1. Have you tested the generated memory compiler from OpenRAM in Cadence/Synopsys Tool?
2. If yes are you getting the 10-20 GHz in the said tools as reported by the Openram output file. We have tried compiling the generated schematic in Cadence Virtuoso but we are only able to get frequency up to 400 MHz?
3. In the Config file, we have tried changing the number of Banks but we are getting only one bank.

Hello mguthaus.
I am at the beginning of most entry.
but when i responded Readme, Unit test clogged up in this part.

For info, 00_code_format_check_test.py is pass, I installed freepdk45 tech. All tool's version is correct : python 2.7.9 also h,ng spice .

01~30(openram total test) are failed. because,,

ERROR: runTest (30_openram_test.openram_test)

Traceback (most recent call last):
File "/home/leepil/OpenRAM-master/compiler/tests/30_openram_test.py", line 23, in runTest
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
File "/home/leepil/OpenRAM-master/compiler/tests/../globals.py", line 113, in init_openram
import_tech()
File "/home/leepil/OpenRAM-master/compiler/tests/../globals.py", line 314, in import_tech
import(filename)
File "/home/leepil/OpenRAM-master/technology/setup_scripts/setup_openram_freepdk45.py", line 16, in
PDK_DIR=os.path.abspath(os.environ.get("FREEPDK45"))
File "/home/leepil/PycellStudio3/plat_linux_gcc44x_64/3rd/lib/python2.7/posixpath.py", line 367, in abspath
if not isabs(path):
File "/home/leepil/PycellStudio3/plat_linux_gcc44x_64/3rd/lib/python2.7/posixpath.py", line 61, in isabs
return s.startswith('/')

AttributeError: 'NoneType' object has no attribute 'startswith'

This error appeared as common between 01 and 30.

can you help me please?

Thank you

In calibre pex mode, the timing cannot be executed correctly:

the measurement statements in the stim.sp file, ran on the pexed file do not work:
for instance: tran v_bl_READ_ZERO0 FIND v(xsram_2_16_freepdk45.xbank0.bl_1) AT=4000.0n

The target is a a node in a subcircuit. However, after PEX, the netlist is flattened and this node is not available as written in the stimulus file.
Two options are possible:

1. The node is available as 'flattened node', so the stimulus writer file needs to be pex-aware and change the net name
2. The calibre pex needs to be ran in 'hierarchical mode', so that the hierarchy is preserved (no idea if this is possible in calibre, I know from experience that this is possible in quantus QRC)

https://github.com/VLSIDA/OpenRAM/projects doesn't resolve

Hello mguthaus,

While am running 04_pinv_test.py for tsmc technology, i am getting an error like
"ERROR: runTest (main.pinv_test)

Traceback (most recent call last):
File "/home/anagar/Templates/rcmc/OpenRAM-master/compiler/tests/04_pinv_test.py", line 24, in runTest
import pinv
File "/home/anagar/Templates/rcmc/OpenRAM-master/compiler/tests/../pinv.py", line 10, in
class pinv(design.design):
File "/home/anagar/Templates/rcmc/OpenRAM-master/compiler/tests/../pinv.py", line 16, in pinv
c = reload(import(OPTS.config.bitcell))
File "/home/anagar/Templates/rcmc/OpenRAM-master/compiler/tests/../bitcell.py", line 6, in
class bitcell(design.design):
File "/home/anagar/Templates/rcmc/OpenRAM-master/compiler/tests/../bitcell.py", line 15, in bitcell
chars = utils.auto_measure_libcell(pins, "cell_6t", GDS["unit"], layer["boundary"])
File "/home/anagar/Templates/rcmc/OpenRAM-master/compiler/tests/../utils.py", line 42, in auto_measure_libcell
cell[str(pin)] = gdsPinToOffset(cell_vlsi.readPin(str(pin)))
File "/home/anagar/Templates/rcmc/OpenRAM-master/compiler/gdsMill/gdsMill/vlsiLayout.py", line 673, in readPin
pin_boundary=[pin_boundary[0]*self.units[0],pin_boundary[1]*self.units[0],pin_boundary[2]*self.units[0],pin_boundary[3]*self.units[0]]
TypeError: unsupported operand type(s) for *: 'NoneType' and 'float'

Ran 1 test in 0.085s

FAILED (errors=1)"

Can you please have a look on it, what i am missing here.

Thanks,
Anuj Nagar

I generated 1024x8 block with scn4m_subm technology. I converted it to tape-out on TSMC 0.35um with some simple layer operations.
I got antenna violations in the replica bitcell. There wordlines of the replica cells are connected directly to GND. As the connections are quite long it gives antenna violations. I solved it by manually adding diodes below the via that connects the wordlines to GND.
In smaller technlogies direct connections to VDD or GND will even be prohibited by the design rules. So I think the proper fix is to introduce a tie low cell for tieing the word lines to ground.

The hierarchical decoder is incorrect in terms of mapping an input address to the correct row. For example, for a 64 row decoder, address 1 mapped to row 16 and address 32 mapped to row 2. Unfortunately, my current decoder has widely diverged from the existing implementation so I can't generate a good enough clean patch.
This gist shows my patch for fixing the issue. At the very least, whatever fix for this issue should pass the included tests. This gist shows the full decoder for reference.

Remove duplicate clock inverter in MS flop design.
Improve aspect ratio. It doesn't need to match the bit-cell...

Has anyone done Monte Carlo simulation of SRAM Memory compiler generated by openRAM in freePDK 45nm? If yes can you share the Monte Carlo files?

A large number of your files have white space at the end of lines. These should be removed and then a check should be added which prevents people from adding it back.

In many DSP applications (stream processing) memories are only accessed sequentially, so instead of using an address decoder a one hot shift register could be used. Dual ports should be available (one write, one read), since reads are generally not performed from the same address as writes, otherwise such a memory would only offer a fixed delay.

I could use such memories in a project a few years ago. Images were processed in a stream, each memory contained a few lines of the image. A single line was written while simultaneously multiple lines were read out and used in a processing kernel (demosaicing, 2D FIR filters, resizing, ...).

In many such applications memory contents are always overwritten very soon, for example in image processing the maximum time the memory would need to retain data would be at most the time between two frames (42ms at 24fps) and at least the time between two lines (in the range of 10us).
This means dynamic memory cells could be used, without redundant refresh logic (present in all commercial 1T memories). Additionally many such applications can tolerate small error rates, so it should be possible to use very small dynamic cells, thus reducing area and power.

I mentioned image processing since memory requirements can be rather high, and since I have experience with it. The same principles can be applied to audio and radio signals. Since many AI systems are area hungry and noise tolerant, the same principles might be applicable there too, and this is a rapidly growing market.

Right now there are only few SAM research articles available and at the time I could find no commercial memory compilers. And I never saw mentioned a combination of SAM and low retention time dynamic memory cells.

See https://help.github.com/en/github/creating-cloning-and-archiving-repositories/licensing-a-repository#detecting-a-license and https://licensee.github.io/licensee/

License detection is working for the https://github.com/VLSIDA/puffery repository for example.

https://github.com/Xyce/Xyce

Xyce (zīs, rhymes with "spice") is an open source, SPICE-compatible, high-performance analog circuit simulator, capable of solving extremely large circuit problems by supporting large-scale parallel computing platforms.

Does it make sense to support Xyce as a simulator in OpenRAM?

The lib file has the min clock period for a data value of 0/1 as the " min_pulse_width_high" and " min_pulse_width_low". This is not correct -- it should be the "timing_type :"minimum_period"" In addition, the data output delay is measured from the rising edge whereas it should actually be the falling edge. The min pulse width should just be 50% of the minimum period since that is what we characterize (for now).

Hello Matt,

I am facing an issue, while i am writing a gds file then gds2writer.py is showing an error like
" writer.writeToFile("sqrin.gds")
File "/home/anagar/work/cwork/pycells/gdsmillPkg/gdsMill/gds2writer.py", line 539, in writeToFile
self.writeGds2()
File "/home/anagar/work/cwork/pycells/gdsmillPkg/gdsMill/gds2writer.py", line 529, in writeGds2
self.writeHeader(); #first, put the header in
File "/home/anagar/work/cwork/pycells/gdsmillPkg/gdsMill/gds2writer.py", line 160, in writeHeader
dbUnits=self.ibmDataFromIeeeDouble((self.layoutObject.info["units"][0]*1e-6/self.layoutObject.info["units"][1])*self.layoutObject.info["units"][1])
TypeError: unsupported operand type(s) for /: 'float' and 'instancemethod' "

I check it with many files like below :-

1. I read a gds file (by VlsiLayout) generated by layout editor tool.
2. I made some changes and generates its gds file
3. Again i read the gds file generated by gds2writer
4. i made some changes and while i am trying to generate gds file by gds2writer that time i am facing
   error.

So i conclude that gds2writer is not able to generate the file if we are reading the gds file generated by gds2writer.

Matt, Can you please help me

Thanks,
Anuj Nagar

Right now, we track whether there are duplicate names of designs to prevent over-writing GDS records. However, we should just make the design class a factory which ensures certain design classes (e.g. ptx, contact, etc.) are reused and others (e.g. custom modules) have unique names. This will prevent duplicate names and can also prevent repeatedly running DRC/LVS for identical designs.

Hello,

I'm trying to generate a 1R1W SRAM. My config file looks like the following:

# Data word size
word_size = 32
# Number of words in the memory
num_words = 128

num_rw_ports = 0
num_r_ports = 1
num_w_ports = 1

# Technology to use in $OPENRAM_TECH
tech_name = "freepdk45"
# Process corners to characterize
process_corners = ["TT"]
# Voltage corners to characterize
supply_voltages = [ 1.1 ]
# Temperature corners to characterize
temperatures = [ 25 ]

# Output directory for the results
output_path = "temp"
# Output file base name
output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name)

# Disable analytical models for full characterization (WARNING: slow!)
analytical_delay = False

# To force this to use calibre for DRC/LVS/PEX
drc_name = "calibre"
lvs_name = "calibre"
pex_name = "calibre"

Here is the error that occurs:

LIB: Characterizing...
ERROR: file simulation.py: line 164: Cannot add write cycle to a read port. Port 1, Write Ports [0]
Traceback (most recent call last):
  File "OpenRAM/compiler/openram.py", line 77, in 
    s.save()
  File "OpenRAM/compiler/sram/sram.py", line 108, in save
    lib(out_dir=OPTS.output_path, sram=self.s, sp_file=sp_file)
  File "OpenRAM/compiler/characterizer/lib.py", line 34, in __init__
    self.characterize_corners()
  File "OpenRAM/compiler/characterizer/lib.py", line 118, in characterize_corners
    self.characterize()
  File "OpenRAM/compiler/characterizer/lib.py", line 125, in characterize
    self.compute_delay()
  File "OpenRAM/compiler/characterizer/lib.py", line 556, in compute_delay
    char_results = self.d.analyze(probe_address, probe_data, self.slews, self.loads)
  File "OpenRAM/compiler/characterizer/delay.py", line 1099, in analyze
    feasible_delays = self.find_feasible_period()
  File "OpenRAM/compiler/characterizer/delay.py", line 692, in find_feasible_period
    feasible_delays[self.read_ports[0]] = self.find_feasible_period_one_port(self.read_ports[0])
  File "OpenRAM/compiler/characterizer/delay.py", line 658, in find_feasible_period_one_port
    (success, results)=self.run_delay_simulation()
  File "OpenRAM/compiler/characterizer/delay.py", line 722, in run_delay_simulation
    self.write_delay_stimulus()
  File "OpenRAM/compiler/characterizer/delay.py", line 407, in write_delay_stimulus
    self.create_test_cycles()
  File "OpenRAM/compiler/characterizer/delay.py", line 1283, in create_test_cycles
    self.gen_test_cycles_one_port(cur_read_port, cur_write_port)
  File "OpenRAM/compiler/characterizer/delay.py", line 1189, in gen_test_cycles_one_port
    write_port)
  File "OpenRAM/compiler/characterizer/simulation.py", line 164, in add_write
    self.write_ports))
  File "OpenRAM/compiler/debug.py", line 32, in check
    assert 0
AssertionError

I get the same result on both the master and dev branches. Any ideas what's going on here?

Thanks in advance!

Thanks for a great tool!

I was just giving it a try and I found out that the example configs in the compiler/example_configs directory aren't fully working. Specifically, I tried the ones for scn4m_subm with check_lvsdrc = True (such as example_config_1rw_1r_scn4m_subm.py) from the current latest dev branch (b7c66d7) and I get the following errors:

ERROR: file magic.py: line 249: sram_1rw_1r_2_16_scn4m_subm     LVS mismatch (results in /home/andresag/Repos/openram_output/snc4m/ports_1rw/analytical/tmp/sram_1rw_1r_2_16_scn4m_subm.lvs.report)
** Verification: 22.5 seconds
** SRAM creation: 36.4 seconds
LEF: Writing to /home/andresag/Repos/openram_test/temp/sram_1rw_1r_2_16_scn4m_subm.lef
** LEF: 0.7 seconds
GDS: Writing to /home/andresag/Repos/openram_test/temp/sram_1rw_1r_2_16_scn4m_subm.gds
** GDS: 0.3 seconds
SP: Writing to /home/andresag/Repos/openram_test/temp/sram_1rw_1r_2_16_scn4m_subm.sp
** Spice writing: 0.1 seconds
LIB: Characterizing... 
ERROR: file magic.py: line 249: sram_1rw_1r_2_16_scn4m_subm     LVS mismatch (results in /home/andresag/Repos/openram_output/snc4m/ports_1rw/analytical/tmp/sram_1rw_1r_2_16_scn4m_subm.lvs.report)
ERROR: file magic.py: line 249: sram_1rw_1r_2_16_scn4m_subm     LVS mismatch (results in /home/andresag/Repos/openram_output/snc4m/ports_1rw/analytical/tmp/sram_1rw_1r_2_16_scn4m_subm.lvs.report)
ERROR: file magic.py: line 249: sram_1rw_1r_2_16_scn4m_subm     LVS mismatch (results in /home/andresag/Repos/openram_output/snc4m/ports_1rw/analytical/tmp/sram_1rw_1r_2_16_scn4m_subm.lvs.report)

The generated files show a few errors here and there. For example setup.tcl and sram_1rw_1r_2_16_scn4m_subm.lvs.err contain:

# Setup file for netgen
ignore class c
equate class {-circuit1 nfet} {-circuit2 n}
equate class {-circuit1 pfet} {-circuit2 p}
# We must flatten these because the ports are disconnected
flatten class {-circuit1 dummy_cell_6t}
flatten class {-circuit1 dummy_cell_1rw_1r}
flatten class {-circuit1 dummy_cell_1w_1r}
flatten class {-circuit1 bitcell_array_0}
flatten class {-circuit1 pbitcell_0}
flatten class {-circuit1 pbitcell_1}
property {-circuit1 nfet} remove as ad ps pd
property {-circuit1 pfet} remove as ad ps pd
property {-circuit2 n} remove as ad ps pd
property {-circuit2 p} remove as ad ps pd
permute transistors

Error setup.tcl:2 (ignoring), No such cell!
Error setup.tcl:6 (ignoring), No such cell or bad file number!
Error setup.tcl:8 (ignoring), No such cell or bad file number!
Error setup.tcl:10 (ignoring), No such cell or bad file number!
Error setup.tcl:11 (ignoring), No such cell or bad file number!

The file sram_1rw_1r_2_16_scn4m_subm.lvs.report also contains a lot of mismatch errors such as this:

Cell write_driver disconnected node: comment_0_0#

Subcircuit summary:
Circuit 1: write_driver                    |Circuit 2: write_driver
-------------------------------------------|-------------------------------------------
nfet (9)                                   |n (9)
pfet (7)                                   |p (7)
Number of devices: 16                      |Number of devices: 16
Number of nets: 16 **Mismatch**            |Number of nets: 13 **Mismatch**
---------------------------------------------------------------------------------------
NET mismatches: Class fragments follow (with fanout counts):
Circuit 1: write_driver                    |Circuit 2: write_driver

---------------------------------------------------------------------------------------

I am using the Ubuntu docker hub image linked from the README.

Do you know what causes these issues?

Thanks for the help!

Right now, each shape must overlap the label/point. If we have adjacent/overlapping shapes, these should also be considered pins.

Power (and some other numbers?) are 0 in the analytical lib file. This should be replaced with switched capacitance P=1/2CV^2f.

The current SRAM design exposes the sense amplifier directly on the output. This means that during precharge the output of DOUT is in undetermined digital state. This is reflected in the verilog code in the following way:

  always @(posedge clk0)
  begin
    ...
    DOUT0 = 8'bx;

This mean that if there is a path from DOUT to the input of a flip-flop that also is clocked on the rising edge, hold violations may occur.
I have to admit I am not a liberty file or STA expert but I don't seem to find the needed data in the .lib that allows to check for this hold violation. I would expect that retain data is needed for DOUT on rising edge of the clock to make this possible.
I am currently targeting 0.35um so with a well controlled skew on the clock tree hold violations should not be a problem but for smaller nodes I think this becomes a necessity.

Dear,
I'm looking for a open source small OpenRom e.g. 256Words 16bit for a custom design.
Has OpenRam team worked on ROM or did the OpenRam team know the availability
I touth Aliance had done some work but I believe its outdated and not loger supported.
Hoping to receive a positive reaction, I meanwhile remain,
Patrick Pelgrims

The link https://join.slack.com/t/openram/shared_invite/enQtNDgxMjc3NzU5NTI1LTE4ODMyM2I0Mzk2ZmFiMjgwYTYyMTQ4NTgwMmUwMDhiM2E1MDViNDRjYzU1NjJhZTQxNWZjMzE3M2FlODBmZjA which is in the README.md fails with the following error;

This invite link is no longer active.
If you have an @ucsc.edu email address, you can still create an account.

If not, please check with the person who shared the invite link with you to ask for an invitation.

Right now this is hard coded. Autodetect ideal number of threads for hspice.

My school currently has only licenses to Synopsys EDA tools.
Would it be possible to have the option to use Synopsys IC Validator for LVS/DRC with FreePDK45?
When using FreePDK45, could any open-source tools be used for LVS/DRC/PEX?

Hey everyone,
I have a problem with the specification of power/timing through the spice simulations. Regardless of the size of the generated SRAM, I get the following error.

Technology: scn4m_subm Total size: 32 bits Word size: 2 Words: 16 Banks: 1 Write size: None RW ports: 1 R-only ports: 0 W-only ports: 0 Design supply routing skipped. Supplies will have multiple must-connect pins. (route_supplies=True to enable supply routing). DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking). DRC/LVS/PEX is disabled (check_lvsdrc=True to enable). Performing simulation-based characterization with ngspice Words per row: 1 Output files are: /home/pi/OpenRAM/temp2x16_noana/sram_2_16_scn4m_subm.sp /home/pi/OpenRAM/temp2x16_noana/sram_2_16_scn4m_subm.v /home/pi/OpenRAM/temp2x16_noana/sram_2_16_scn4m_subm.lib /home/pi/OpenRAM/temp2x16_noana/sram_2_16_scn4m_subm.py /home/pi/OpenRAM/temp2x16_noana/sram_2_16_scn4m_subm.html /home/pi/OpenRAM/temp2x16_noana/sram_2_16_scn4m_subm.log /home/pi/OpenRAM/temp2x16_noana/sram_2_16_scn4m_subm.lef /home/pi/OpenRAM/temp2x16_noana/sram_2_16_scn4m_subm.gds ** Submodules: 1.6 seconds ** Placement: 0.0 seconds ** Routing: 0.1 seconds ** Verification: 0.0 seconds ** SRAM creation: 1.8 seconds LEF: Writing to /home/pi/OpenRAM/temp2x16_noana/sram_2_16_scn4m_subm.lef ** LEF: 1.0 seconds GDS: Writing to /home/pi/OpenRAM/temp2x16_noana/sram_2_16_scn4m_subm.gds ** GDS: 0.5 seconds SP: Writing to /home/pi/OpenRAM/temp2x16_noana/sram_2_16_scn4m_subm.sp ** Spice writing: 0.0 seconds LIB: Characterizing... ERROR: file delay.py: line 1141: Couldn't run a simulation. slew=0.05 load=2.45605
Thanks for your help.
Yannick

Issue: Bug
Severity: High
Description: When I generate a default SRAM from your example for the latest gscl45 with -n option, the output verilog has OEb pin, which is NOT available in the liberty output. This results in a synthesis fail when I synthesize a wrapper for the generated memory. Pls fix this

During my work with the openram layout, I encountered a strange behaviour of the Sense Amplifier enable signal. For me, it looks like the enable signal is only active during the writes (S_en = web and (not csb) and (not clk) ). That means that the output voltage is not stable when you try to read from the SRAM. Is it possible that there is a mistake in the control logic?

Will you add any FinFET 15nm PDK technology support for the tool?

Thank you.

The analytical delay mode should just output some constants.

Hi,

Thank you for your hard work on OpenRAM.

We are using your tool for the generation of a single-port cache tag storage with quite unusual specifications (25-bit words with usual 8-bit bytes) and encountered an issue: Usually, if word_size is not multiple of write_size, one would expect that the num_wmasks is rounded up so that all bits are covered. In our case, this would mean that the final word bit 24 has a strobe of its own.

Unfortunately in OpenRAM, the following rounding down is done:

int(self.word_size / self.write_size)

meaning that the "remainder" bits in a word have no enable at all. I see there is an argument to be made that this should be handled in a different way than our proposal, but the current state is not desirable in any case as the upper bits effectively cannot be written to.

Here is a quick patch fixing the verilog wrapper and LIB files; I believe the other outputs would need further work (especially Spice and LVS): patch.txt

Best regards

Each route right now is point-to-point. We can route multiple point-to-point routes, but not multiple pin nets. Add support for a steiner tree, etc.

Change the delay measurement to be from the negative clock edge to
remove the dependency on the clock period.

Make lib file have delay relative to negedge for DATA.

Right now, scn3me_subm has reasonable labels, but freepdk45 labels are too large.

I generated a 1024x8 SRAM block with the scn4m_subm technology. When looking at the LEF files the (input) pins don't seem to be accessible for P&R.
The flip-flops have an OBS on metal1 and metal2 and on metal3 and metal4 the GND/VDD grid is generated.
My design was just test chip with an OpenRAM block, I circumvented the problem by manual connecting the pins out of the block.

Is it in the current version possible to create a SRAM with more then one bank? I already tried to add "num_banks = 2" to my "myconfig.py" file. But this always results in a layout with only one bank. Also i already saw that the number of banks is not passed to "sram_config". Does that mean that multi bank is not supported yet?

I am having problems compiling a multiport SRAM with 1 read-write port and 1 read-only port. I am using the following config:

word_size = 2                                                                       
num_words = 16                                                                      
                                                                                    
num_rw_ports = 1                                                                    
num_r_ports = 1                                                                     
num_w_ports = 0                                                                     
                                                                                    
tech_name = "freepdk45"                                                             
nominal_corners_only = False                                                        
process_corners = ["TT"]                                                            
supply_voltages = [1.0]                                                             
temperatures = [25]                                                                 
                                                                                    
route_supplies = False                                                              
check_lvsdrc = False                                                                
                                                                                    
analytical_delay = False                                                            
                                                                                    
purge_temp = False                                                                  
                                                                                    
output_path = "."                                                                   
output_name = "sram_{0}_{1}_{2}".format(word_size, num_words, tech_name)                                                                                            

The problem is that the function parse_spice_list() is failing to parse the delay_sen1 measurement from the tmp/timing.lis file, i.e the output file from ngspice, when analysing the delays for read port 1. This is the error message in timing.lis:

Error: measure  delay_sen1  (TARG) : out of interval
.meas tran delay_sen1 trig v(clk1) val=0.5 fall=1 td=27.5n targ v(xsram_2_16_freepdk45.s_en0) val=0.5 rise=1 td=27.5n failed!

Unfortunately, the error was not caught earlier and parse_spice_list() continuously returns the string "Failed" rather than a floating-point number. This then causes the try_period() function to repeatedly fail, which in turn, forces find_min_period_one_port() into an infinite loop until a timeout occurs here.

Do you know how I can get around the problem with ngspice? Thanks!

Add support for Magic for DRC and netgen for LVS of SCMOS technolgoies.

It would be good if there was a documentation page which had a list of papers which use OpenRAM or similar.

This issue is intended to keep track of the work on the pin driven signal routing

• Add layer class
  • name
  • layer stack index
  • tech layer number/purpose)
• Interconnect_stack class
  • contains connections between layers
  • get_layers(l1, l2) returns list of complete stack to get from l1 to l2, For instance get_layers(m1, m3) returns [(m1, via1, m2), (m2, via2, m3)
• route_pins(pin1, pin2) function using wire class
  • tries to match the layers of both pins:
    • If there is a jog, punch a via stack on the corner and try to obey the metal layer direction
    • If it is a straight connection, punch the lower pin onto the layer of the upper
• Convert the signal path of custom cells to use the route_pins api
  • dff
  • bitcell
  • sense_amp
  • write_driver

I get the attribute error and the script stops there. If I use one bank, it runs smoothly, but I want to create larger memory. Do I have to set the attribute for object manually?

Technology: FreePDK45
Total size: 512 bits
Word size: 8
Words: 32
Banks: 2
Write size: None
RW ports: 1
R-only ports: 0
W-only ports: 0
Design supply routing skipped. Supplies will have multiple must-connect pins. (route_supplies=True to enable supply routing).
DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).
DRC/LVS/PEX is disabled (check_lvsdrc=True to enable).
Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate).
Only characterizing nominal corner.
Words per row: 1
Traceback (most recent call last):
File "/home/jkhan/openram/compiler/openram.py", line 77, in
s = sram(sram_config=c,
File "/home/jkhan/openram/compiler/sram/sram.py", line 44, in __init__
self.s.create_netlist()
File "/home/jkhan/openram/compiler/sram/sram_base.py", line 96, in create_netlist
self.add_modules()
File "/home/jkhan/openram/compiler/sram/sram_2bank.py", line 61, in add_modules
self.compute_bus_sizes()
File "/home/jkhan/openram/compiler/sram/sram_base.py", line 173, in compute_bus_sizes
self.num_vertical_line = self.addr_size + self.control_size + log(self.num_banks, 2) + 1
AttributeError: 'sram_2bank' object has no attribute 'control_size'

The gds and sp files were not present in the temporary folder when running calibre pex. See pull request.

Cell name (ms_flop) is hard coded in characterizer, pin names are hard
coded too. This should come from the config file which dynamically
loads the module names.

The test is incredibly complicated and repeats code that is already in the characterizer. Test is skipped right now.

If you get shapes using the method getAllPinShapesInStructureList, you will get two of every shape. It is unclear why this is. A simple example is using the router test 01_no_blockages_test.py (with -v -v) which will output these shapes:

[ find_pin ]: Find pin p(1040, 8198)_11 layer 11 shape [mpf('0.38250000000000001'), mpf('3.8925000000000001'), mpf('0.745'), mpf('4.2149999999999999')]

[ find_pin ]: Find pin p(1040, 8198)_11 layer 11 shape [mpf('0.1125'), mpf('3.9875000000000003'), mpf('1.2725'), mpf('4.1524999999999999')]

[ find_pin ]: Find pin p(1040, 8198)_11 layer 11 shape [mpf('0.45000000000000001'), mpf('3.6475'), mpf('0.67500000000000004'), mpf('4.1275000000000004')]

[ find_pin ]: Find pin p(1040, 8198)_11 layer 11 shape [mpf('0.38250000000000001'), mpf('3.8925000000000001'), mpf('0.745'), mpf('4.2149999999999999')]

[ find_pin ]: Find pin p(1040, 8198)_11 layer 11 shape [mpf('0.1125'), mpf('3.9875000000000003'), mpf('1.2725'), mpf('4.1524999999999999')]

[ find_pin ]: Find pin p(1040, 8198)_11 layer 11 shape [mpf('0.45000000000000001'), mpf('3.6475'), mpf('0.67500000000000004'), mpf('4.1275000000000004')]

which is three pins replicated twice.