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algorithms

amba

Amba interconnect library

bio

buraq-mini

This repository contains the 5 stage pipelined CPU implemented on the RISC-V ISA and Chisel hardware construction language (HDL)

calculating-bitcoin-beta

Calculating the bitcoin beta using the linear regression model

caravan

A caravan equipped with API for creating bus protocols in Chisel with ease.

caravel_ibtida_soc

chisel-circt

chisel-intermediate

chisel-noc-generator

This is a final project for CSE 228A "Agile Hardware Design" at UC Santa Cruz

chisel3

Chisel 3: A Modern Hardware Design Language

chisel3-wiki

crypto-analysis

Analysis of crypto currency

crypto-arbitrage

Cryptocurrency Arbitrage with Python

cse211-fa2022

Class website for CSE 211 at UCSC for the fall 2022 quarter

dotfile

dromajo

RISC-V RV64GC emulator designed for RTL co-simulation

firrtl

Flexible Intermediate Representation for RTL

gdb-stub

This is an implementation of a GDB stub later to be used inside Dromajo to give it the GDB support

hadirkhan10

hadirkhan10.github.io

hw1

HW1 for Agile Hardware Design

ibtida-ii

https://caravel-user-project.readthedocs.io

jigsaw

A platform containing useful peripherals implemented in Chisel that can be attached together to complete the puzzle (SoC).

memcompose

mpt-on-stock

Modern Portfolio Theory with Stock Data

openfabric

Open source generator for creating customisable bus topologies (Point-to-point, Shared Bus, CrossBar Switch) based on the bus protocol type provided by the user (AHB, Wishbone, TileLink)

openlane-gui

A graphical user interface for the OpenLANE RTL-GDSII flow

opentitan

OpenTitan: Open source silicon root of trust

picofoxy

Pipelined In-order Core for Artix-7 Arty-35T board