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amaranth

A modern hardware definition language and toolchain based on Python

ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core

cfu-playground

Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online workshop: https://google.github.io/CFU-Playground/ For reference docs, see the link below.

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

esp

Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

naxriscv

nngen

NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network

ntnu-firesim

FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation in the Cloud

proteus

The SpinalHDL design of the Proteus core, an extensible RISC-V core.

riscv-ocelot

Ocelot: The Berkeley Out-of-Order Machine With V-EXT support

riscv-vector-tests

The missing test suite for RISC-V V extension.

riscv_vhdl

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

rocket-chip-vcu128

Run Rocket Chip on VCU128

shuttle

A Rocket-based RISC-V superscalar in-order core

tinygrad

You like pytorch? You like micrograd? You love tinygrad! ❤️

v2chisel

verilog-axi

Verilog AXI components for FPGA implementation

verilog-ethernet

Verilog Ethernet components for FPGA implementation

verilog-pcie

Verilog PCI express components

vicuna

RISC-V Zve32x Vector Coprocessor

vroom

VRoom! RISC-V CPU

xiangshan

Open-source high-performance RISC-V processor