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a2g

Analog layout generator

align-pdk-sky130

align-public

amaranth

A modern hardware definition language and toolchain based on Python

amaranth-tutorial

analog-mixed-signal-simulation-and-modeling

This is my labs for the AMS simulation and modeling Training of Siemens EDA in Summer 2022, delivered by Dr. Hesham Omran.

arxivpapers

Code behind Arxiv Papers

astran

ASTRAN - Automatic Synthesis of Transistor Networks

autockt

Deep Reinforcement Learning of Analog Circuit Designs

examples

Pre-built mlpack models

extension-summarize-translate-gemini

Chrome extension to summarize and translate web pages. Uses Gemini as the backend.

gpt-researcher

GPT based autonomous agent that does online comprehensive research on any given topic

hdlgen-chatgpt

HDLGen-ChatGPT, works in tandem with ChatGPT-3.5 chat interface to enable fast digital systems design and test specification capture, and automatic generation of both VHDL and Verilog models, and testbenches, and AMD Vivado and Intel Quartus Electronic Design Automation (EDA) project

hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

hwtlib

hardware library for hwt (= ipcore repo)

jira_testcase

kiwi

the leading open source test case management system

lcapy-gui

A graphical user interface for symbolic circuit analysis using Lcapy

mg-verilog

ml4dv

LLM4DV

oh

Verilog library for ASIC and FPGA designers

ollama

Get up and running with Llama 2, Mistral, and other large language models locally.

polyphony

Polyphony is Python based High-Level Synthesis compiler.

pygears

HW Design: A Functional Approach

pygmid

A python3 gm/ID starter kit

pyserdes

ralf

Reinforcement learning assisted analog layout design flow.

redcase

Test case management plug-in for the Redmine

redmine_auto_watchers_from_groups

redmine_impasse

The redmine plugin for test management.