vijayan's Projects
AES128 design submission for GF180 MPW0 Shuttle
This repository is the GF180MCU port of Caravel. For more information about Caravel, see the original repo at https://github.com/efabless/caravel.
Material for OpenROAD Tutorial at DAC 2020
DSP Processor for GF180 MPW shuttle
MPW7 resubmission
an inverter drawn in magic with makefile to simulate
PDK installer for open-source EDA tools and toolchains. Distributed with a setup for the Google/SkyWater 130nm process.
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
An open-source static random access memory (SRAM) compiler.
OpenROAD's unified application implementing an RTL-to-GDS Flow
Submission template for Tiny Tapeout 04
RTL Design using Verilog Hardware Description Language
Config files for my GitHub profile.