Comments (11)
mguthaus
commented on August 16, 2024
Hi,
Which technology are you running? Can you provide more information so that
we can replicate this?
…On Nov 23, 2016 10:44 PM, "Anuj Nagar" ***@***.***> wrote:
Hello mguthaus,
While am running 04_pinv_test.py for tsmc technology, i am getting an
error like
"ERROR: runTest (*main*.pinv_test)
Traceback (most recent call last):
File "/home/anagar/Templates/rcmc/OpenRAM-master/compiler/tests/04_pinv_test.py",
line 24, in runTest
import pinv
File "/home/anagar/Templates/rcmc/OpenRAM-master/compiler/tests/../pinv.py",
line 10, in
class pinv(design.design):
File "/home/anagar/Templates/rcmc/OpenRAM-master/compiler/tests/../pinv.py",
line 16, in pinv
c = reload(*import*(OPTS.config.bitcell))
File "/home/anagar/Templates/rcmc/OpenRAM-master/compiler/tests/../bitcell.py",
line 6, in
class bitcell(design.design):
File "/home/anagar/Templates/rcmc/OpenRAM-master/compiler/tests/../bitcell.py",
line 15, in bitcell
chars = utils.auto_measure_libcell(pins, "cell_6t", GDS["unit"],
layer["boundary"])
File "/home/anagar/Templates/rcmc/OpenRAM-master/compiler/tests/../utils.py",
line 42, in auto_measure_libcell
cell[str(pin)] = gdsPinToOffset(cell_vlsi.readPin(str(pin)))
File "/home/anagar/Templates/rcmc/OpenRAM-master/compiler/
gdsMill/gdsMill/vlsiLayout.py", line 673, in readPin
pin_boundary=[pin_boundary[0]*self.units[0],pin_boundary[1]*
self.units[0],pin_boundary[2]*self.units[0],pin_boundary[3]*self.units[0]]
TypeError: unsupported operand type(s) for *: 'NoneType' and 'float'
------------------------------
Ran 1 test in 0.085s
FAILED (errors=1)"
Can you please have a look on it, what i am missing here.
Thanks,
Anuj Nagar
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mguthaus
commented on August 16, 2024
Also,
Please make sure you are using the most recent version. Can you send us the
output is git log?
…On Nov 23, 2016 10:44 PM, "Anuj Nagar" ***@***.***> wrote:
Hello mguthaus,
While am running 04_pinv_test.py for tsmc technology, i am getting an
error like
"ERROR: runTest (*main*.pinv_test)
Traceback (most recent call last):
File "/home/anagar/Templates/rcmc/OpenRAM-master/compiler/tests/04_pinv_test.py",
line 24, in runTest
import pinv
File "/home/anagar/Templates/rcmc/OpenRAM-master/compiler/tests/../pinv.py",
line 10, in
class pinv(design.design):
File "/home/anagar/Templates/rcmc/OpenRAM-master/compiler/tests/../pinv.py",
line 16, in pinv
c = reload(*import*(OPTS.config.bitcell))
File "/home/anagar/Templates/rcmc/OpenRAM-master/compiler/tests/../bitcell.py",
line 6, in
class bitcell(design.design):
File "/home/anagar/Templates/rcmc/OpenRAM-master/compiler/tests/../bitcell.py",
line 15, in bitcell
chars = utils.auto_measure_libcell(pins, "cell_6t", GDS["unit"],
layer["boundary"])
File "/home/anagar/Templates/rcmc/OpenRAM-master/compiler/tests/../utils.py",
line 42, in auto_measure_libcell
cell[str(pin)] = gdsPinToOffset(cell_vlsi.readPin(str(pin)))
File "/home/anagar/Templates/rcmc/OpenRAM-master/compiler/
gdsMill/gdsMill/vlsiLayout.py", line 673, in readPin
pin_boundary=[pin_boundary[0]*self.units[0],pin_boundary[1]*
self.units[0],pin_boundary[2]*self.units[0],pin_boundary[3]*self.units[0]]
TypeError: unsupported operand type(s) for *: 'NoneType' and 'float'
------------------------------
Ran 1 test in 0.085s
FAILED (errors=1)"
Can you please have a look on it, what i am missing here.
Thanks,
Anuj Nagar
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anujnagar
commented on August 16, 2024
TSMC technology i am using.
Where i can get this git log output?
I was running the test case for 04_pinv_test.py. It was asking for bitcell gds file thn i copied gds file to gds_lib dir and again i ran it. After that it gave me the above error.
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mguthaus
commented on August 16, 2024
Hi Anuj,
The 04_pinv_test.py requires a bitcell to be defined and passing in order
to match the bitcell height. You should get the tests passing in order by
starting with test 00, 01, etc. Does test 01 pass? Though, this doesn't
attempt to measure read the pins of the bitcell, so you may not see the
error with that cell until test 04.
The bitcell likely doesn't pass if you did not create the correct labels
for all pins. The pin names are defined in the technology file. I agree
that this error message is cryptic and we will add a better one.
Matt
…On Sun, Nov 27, 2016 at 11:24 PM, Anuj Nagar ***@***.***> wrote:
TSMC technology i am using.
Where i can get this git log output?
I was running the test case for 04_pinv_test.py. It was asking for bitcell
gds file thn i copied gds file to gds_lib dir and again i ran it. After
that it gave me the above error.
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Associate Professor, Computer Engineering
CE Undergraduate Program Director
University of California Santa Cruz
http://www.soe.ucsc.edu/~mrg
http://vlsida.soe.ucsc.edu/
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anujnagar
commented on August 16, 2024
Does port name should match with freepdk45 bitcell ?
Anyhow if here we are using bit cell for height only thn port matching doesn't make sense.
Okay i will check it again and i will let you know.
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mguthaus
commented on August 16, 2024
There are example names provided in the freepdk45 bitcell. You can change
the names in the technology file. There may be places that these are
hard-coded so it is best to follow the same names. However, we would like
to ensure they aren't hard coded in the future.
We need to ensure that we can make an inverter that matches the pitch of
the bitcell. If not, this test should fail because we won't be able to make
an SRAM.
…On Mon, Nov 28, 2016 at 8:59 AM, Anuj Nagar ***@***.***> wrote:
Does port name should match with freepdk45 bitcell ?
Anyhow if here we are using bit cell for height only thn port matching
doesn't make sense.
Okay i will check it again and i will let you know.
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CE Undergraduate Program Director
University of California Santa Cruz
http://www.soe.ucsc.edu/~mrg
http://vlsida.soe.ucsc.edu/
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anujnagar
commented on August 16, 2024
one more thing, how can i check the code version.
I mean how can i check which version i am using.
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mguthaus
commented on August 16, 2024
If you cloned from github, you should use git by typing:
git log
and see the most recent commit hash. Right now, the master (released copy)
is at:
commit d195df6
…On Mon, Nov 28, 2016 at 9:02 AM, Anuj Nagar ***@***.***> wrote:
one more thing, how can i check the code version.
I mean how can i check which version i am using.
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Matthew Guthaus
Associate Professor, Computer Engineering
CE Undergraduate Program Director
University of California Santa Cruz
http://www.soe.ucsc.edu/~mrg
http://vlsida.soe.ucsc.edu/
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anujnagar
commented on August 16, 2024
Hello Matt,
Is there any way to generate spuce and verilog only.
If we don't have layout of basic leaf cells. Cant we get spice and verilog for simple circuit verification.
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mguthaus
commented on August 16, 2024
Sorry:
commit 2d0533a
I was on a different branch.
On Mon, Nov 28, 2016 at 9:04 AM, Matt Guthaus <[email protected]>
wrote:
… If you cloned from github, you should use git by typing:
git log
and see the most recent commit hash. Right now, the master (released copy)
is at:
commit d195df6
On Mon, Nov 28, 2016 at 9:02 AM, Anuj Nagar ***@***.***>
wrote:
> one more thing, how can i check the code version.
> I mean how can i check which version i am using.
>
> —
> You are receiving this because you commented.
> Reply to this email directly, view it on GitHub
> <https://github.com/mguthaus/OpenRAM/issues/9#issuecomment-263328508>,
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AL35L9EA8aRDIICIWQaTLd67Kw5wZyynks5rCwkggaJpZM4K7U5p>
> .
>
--
Matthew Guthaus
Associate Professor, Computer Engineering
CE Undergraduate Program Director
University of California Santa Cruz
http://www.soe.ucsc.edu/~mrg
http://vlsida.soe.ucsc.edu/
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Associate Professor, Computer Engineering
CE Undergraduate Program Director
University of California Santa Cruz
http://www.soe.ucsc.edu/~mrg
http://vlsida.soe.ucsc.edu/
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mguthaus
commented on August 16, 2024
Hi Anuj,
That is not currently an option, but we could add it as a feature request.
…On Mon, Nov 28, 2016 at 9:06 AM, Anuj Nagar ***@***.***> wrote:
Hello Matt,
Is there any way to generate spuce and verilog only.
If we don't have layout of basic leaf cells. Cant we get spice and verilog
for simple circuit verification.
—
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--
Matthew Guthaus
Associate Professor, Computer Engineering
CE Undergraduate Program Director
University of California Santa Cruz
http://www.soe.ucsc.edu/~mrg
http://vlsida.soe.ucsc.edu/
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