Comments (6)
cannotgetaname
commented on August 16, 2024
me too
I run in freepdk45 with 2 banks.
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c-93
commented on August 16, 2024
I am getting a similar error without touching the bank configuration, by just increasing the memory size of the single port tiny example to an arbitrary (?) size. Here is an example config, which fails for me.
word_size = 32 # Bits
num_words = 256
human_byte_size = "{:.0f}kbytes".format((word_size * num_words)/1024/8)
# Allow byte writes
write_size = 8 # Bits # does not matter
# Single port
num_rw_ports = 1 #one rw port will provoque the error
num_r_ports = 0
num_w_ports = 0
num_spare_rows = 1
num_spare_cols = 1
ports_human = '1rw'
import os
exec(open(os.path.join(os.path.dirname(__file__), 'sky130_sram_common.py')).read())Tail, of a massive 256mb log file:
[2024-03-22 14:44:26.112289] [openram.verify.magic/run_lvs]: Instance: sky130_sram_1kbyte_1rw_32x256_8_bank_0//sky130_sram_1kbyte_1rw_32x256_8_sky130_capped_replica_bitcell_array_0// |Instance: sky130_sram_1kbyte_1rw_32x256_8_bank:bank0/sky130_sram_1kbyte_1rw_32x256_8_sky130_capped_replica_bitcell_array:
[2024-03-22 14:44:26.112484] [openram.verify.magic/run_lvs]: (1,3) = (52787,2) | (1,3) = (52528,2)
[2024-03-22 14:44:26.112677] [openram.verify.magic/run_lvs]: 2 = 2 | 2 = 2
[2024-03-22 14:44:26.112874] [openram.verify.magic/run_lvs]: 4 = 52787 | 4 = 52528
[2024-03-22 14:44:26.113116] [openram.verify.magic/run_lvs]: |
[2024-03-22 14:44:26.113338] [openram.verify.magic/run_lvs]: (no matching instance) |Instance: sky130_sram_1kbyte_1rw_32x256_8_bank:bank0/sky130_sram_1kbyte_1rw_32x256_8_sky130_capped_replica_bitcell_array:
[2024-03-22 14:44:26.113624] [openram.verify.magic/run_lvs]: | (1,3) = (52528,2)
[2024-03-22 14:44:26.113880] [openram.verify.magic/run_lvs]: | 2 = 2
[2024-03-22 14:44:26.114095] [openram.verify.magic/run_lvs]: | 4 = 52528
[2024-03-22 14:44:26.114294] [openram.verify.magic/run_lvs]: |
[2024-03-22 14:44:26.114491] [openram.verify.magic/run_lvs]: |
[2024-03-22 14:44:26.114689] [openram.verify.magic/run_lvs]: (no matching instance) |Instance: sky130_sram_1kbyte_1rw_32x256_8_bank:bank0/sky130_sram_1kbyte_1rw_32x256_8_sky130_capped_replica_bitcell_array:
[2024-03-22 14:44:26.114908] [openram.verify.magic/run_lvs]: | (1,3) = (52528,2)
[2024-03-22 14:44:26.115106] [openram.verify.magic/run_lvs]: | 2 = 2
[2024-03-22 14:44:26.115302] [openram.verify.magic/run_lvs]: | 4 = 52528
[2024-03-22 14:44:26.115497] [openram.verify.magic/run_lvs]: |
[2024-03-22 14:44:26.115693] [openram.verify.magic/run_lvs]: -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
[2024-03-22 14:44:26.115893] [openram.verify.magic/run_lvs]: Netlists do not match.
[2024-03-22 14:44:26.116090] [openram.verify.magic/run_lvs]:
[2024-03-22 14:44:26.116287] [openram.verify.magic/run_lvs]: Subcircuit pins:
[2024-03-22 14:44:26.116483] [openram.verify.magic/run_lvs]: Circuit 1: sky130_sram_1kbyte_1rw_32x256_8 |Circuit 2: sky130_sram_1kbyte_1rw_32x256_8
[2024-03-22 14:44:26.116677] [openram.verify.magic/run_lvs]: --------------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------
[2024-03-22 14:44:26.116875] [openram.verify.magic/run_lvs]: vccd1 |(no matching pin)
[2024-03-22 14:44:26.117073] [openram.verify.magic/run_lvs]: vssd1 |(no matching pin)
[2024-03-22 14:44:26.117269] [openram.verify.magic/run_lvs]: dout0[32] |dout0[32]
[2024-03-22 14:44:26.117465] [openram.verify.magic/run_lvs]: dout0[0] |dout0[0]
[2024-03-22 14:44:26.117660] [openram.verify.magic/run_lvs]: dout0[1] |dout0[1]
[2024-03-22 14:44:26.117858] [openram.verify.magic/run_lvs]: dout0[2] |dout0[2]
[I cropped some lines]
[2024-03-22 14:44:26.133741] [openram.verify.magic/run_lvs]: spare_wen0 |(no matching pin)
[2024-03-22 14:44:26.133945] [openram.verify.magic/run_lvs]: (no matching pin) |spare_wen0
[2024-03-22 14:44:26.134144] [openram.verify.magic/run_lvs]: (no matching pin) |vccd1
[2024-03-22 14:44:26.134340] [openram.verify.magic/run_lvs]: (no matching pin) |vssd1
[2024-03-22 14:44:26.134538] [openram.verify.magic/run_lvs]: spare_wen0 |(no matching pin)
[2024-03-22 14:44:26.134734] [openram.verify.magic/run_lvs]: vccd1 |(no matching pin)
[2024-03-22 14:44:26.134934] [openram.verify.magic/run_lvs]: vssd1 |(no matching pin)
[2024-03-22 14:44:26.135132] [openram.verify.magic/run_lvs]: -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
[2024-03-22 14:44:26.135329] [openram.verify.magic/run_lvs]: Cell pin lists for sky130_sram_1kbyte_1rw_32x256_8 and sky130_sram_1kbyte_1rw_32x256_8 altered to match.
[2024-03-22 14:44:26.135525] [openram.verify.magic/run_lvs]: Device classes sky130_sram_1kbyte_1rw_32x256_8 and sky130_sram_1kbyte_1rw_32x256_8 are equivalent.
[2024-03-22 14:44:26.135721] [openram.verify.magic/run_lvs]:
[2024-03-22 14:44:26.135920] [openram.verify.magic/run_lvs]: Final result: Top level cell failed pin matching.
[2024-03-22 14:44:26.136130] ERROR: file magic.py: line 385: sky130_sram_1kbyte_1rw_32x256_8 LVS mismatch (results in OpenRAM/macros2/sky130_sram_1kbyte_1rw_32x256_8/tmp/sky130_sram_1kbyte_1rw_32x256_8.lvs.report)
[2024-03-22 14:44:26.172394] ** Verification: 14516.4 seconds
[2024-03-22 14:44:26.172526] ** SRAM creation: 15336.3 seconds
[2024-03-22 14:44:26.172561] SP: Writing to OpenRAM/macros2/sky130_sram_1kbyte_1rw_32x256_8/sky130_sram_1kbyte_1rw_32x256_8.sp
[2024-03-22 14:44:26.265993] [openram.characterizer.functional/__init__]: Random seed for functional simulation: 1711115066265554705
[2024-03-22 14:44:26.292235] ** Spice writing: 0.1 seconds
[2024-03-22 14:44:26.292334] DELAY: Writing stimulus...
[2024-03-22 14:44:26.543349] ERROR: file simulation.py: line 605: Could not find bl net in timing paths.
The LVS process fails at verifying the netlist as signals/ networks are missing.
Note the no matching instance and no matching pin errors. Maybe signals got renamed?
edit: manually condensed the log even more
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tvd040562
commented on August 16, 2024
Any resolution to this issue?
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c-93
commented on August 16, 2024
No, we switched to DffRam for now.
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tarunkothuri
commented on August 16, 2024
Is there any update on this issue?
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mguthaus
commented on August 16, 2024
No, nobody has been working on it so if you have a fix, we will gladly accept it.
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