Comments (3)
mguthaus
commented on August 16, 2024
OpenRAM uses two things for the width and height:
- If you specify a boundary shape, it will use this. This can have shapes extending outside of it, etc.
- If no boundary is provided, it uses the bounding box of all the shapes.
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YWJ226
commented on August 16, 2024
Thank you for your guidance. May I ask how I should specify the boundary shape? Should I specify the boundary shape when drawing the layout, or do I need to modify a parameter within the OpenRAM code?
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YWJ226
commented on August 16, 2024
Hello, I'm sorry to bother you again. I have encountered another issue now. I have read your article from 2013: "OpenRAM: An Open-Source Memory Compiler," which mentions, "The two major considerations while designing the sense amplifier cell are the size of the cell and the bit line/input pitches." Could you please advise on how to align the bit line inputs of the sense amplifier with the outputs of the write driver? I have already adjusted the pitch of BL to be the same, but I still encounter metal2 connection errors, as shown in the diagram below.
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Related Issues (20)
- openram.py doesn't exist in any tree HOT 1
- Error in SRAM creation with banks HOT 6
- Support for PROBE PDK HOT 4
- ROM dump + replace contents
- ROM >= 8k fails to build HOT 3
- multiports bitcell HOT 1
- Stimuli Generation - sram_func.py or gen_stimuli.py
- Importing a custom GDS file. HOT 7
- Routing error due to high (vertical) density? HOT 1
- No liberty file is created for ROMs HOT 2
- Question: What is the correct allignment in SKY130? Intermediate Pins are not connected to the grid. Likely user mistake. HOT 10
- Errors hidden on default loglevel, but visible on verbose loglevels.
- Support for ASAP7 PDK HOT 1
- Power estimation seems too high HOT 14
- Possible minor error on the documentation related with the ROM usage
- Not generate certain module HOT 1
- Runtime HOT 8
- Adding and Removing Modules and Customizing Module Ports HOT 3
- Error in using sram macro(tiny) in openlane2 HOT 3
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