Comments (5)
mguthaus
commented on July 17, 2024
Hi,
It seems that maybe you have not defined the FREEPDK45 directory to point
to the PDK directory? Can you send what it is defined as in your
environment?
echo $FREEPDK45
echo $OPENRAM_TECH
echo $OPENRAM_HOME
Matt
…On Wed, Aug 16, 2017 at 7:47 PM, leepil ***@***.***> wrote:
Closed #28 <https://github.com/mguthaus/OpenRAM/issues/28>.
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University of California Santa Cruz
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leepil
commented on July 17, 2024
Thank you for the reply.
In setpaths.csh...
$setenv OPENRAM_HOME /home/leepil/OpenRAM-master/compiler
$setenv OPENRAM_TECH /home/leepil/OpenRAM-master/technology
$setenv FREEPDK45 /home/leepil/OpenRAM-master/technology/freepdk45
You used pwd, but I set the path directly.
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mguthaus
commented on July 17, 2024
Did you source this file in your shell? Are the variables actually set?
Please run the commands that I suggested to confirm.
…On Aug 21, 2017 19:35, "leepil" ***@***.***> wrote:
Thank you for the reply.
In setpaths.csh...
$setenv OPENRAM_HOME /home/leepil/OpenRAM-master/compiler
$setenv OPENRAM_TECH /home/leepil/OpenRAM-master/technology
$setenv FREEPDK45 /home/leepil/OpenRAM-master/technology/freepdk45
You used pwd, but I set the path directly.
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leepil
commented on July 17, 2024
That's true! You taght me that " I will not change the code given.". Thx
but... A new error occurred. I obviously made 'calibre' set correctly(of course, i am accurate within knowledge i know).
$Traceback (most recent call last):
$ File "/home/leepil/OpenRAM-master/compiler/tests/20_sram_1bank_test.py", line 31, in runTest
$ self.local_check(a)
$ File "/home/leepil/OpenRAM-master/compiler/tests/20_sram_1bank_test.py", line 42, in local_check
$ self.assertFalse(calibre.run_drc(a.name, tempgds))
$ File "/home/leepil/OpenRAM-master/compiler/tests/../calibre.py", line 116, in run_drc
$ debug.error("Unable to retrieve DRC results file. Is calibre set up?",1)
$ File "/home/leepil/OpenRAM-master/compiler/tests/../debug.py", line 24, in error
$ sys.exit(return_value)
$SystemExit: 1
This error is commonly shown for about 10 tests.
p.s
(I tried to solve openram in the course of two months after I wanted to run openram, but I would like to inform you that it was not done. I also saw the caliber related error I showed as I had already seen. Finally, I ask for help if I can not solve it at all. Thank you very much.)
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mguthaus
commented on July 17, 2024
Check the OpenRAM temp directory for the output from Calibre. This is
discussed in the presentation for how to debug. This is likely a problem
running (or getting a license for ( Calibre.
…On Aug 22, 2017 19:00, "leepil" ***@***.***> wrote:
That's true! You taght me that " I will not change the code given.". Thx
but... A new error occurred. I obviously made 'calibre' set correctly(of
course, i am accurate within knowledge i know).
Traceback (most recent call last):
File "/home/leepil/OpenRAM-master/compiler/tests/20_sram_1bank_test.py",
line 31, in runTest
self.local_check(a)
File "/home/leepil/OpenRAM-master/compiler/tests/20_sram_1bank_test.py",
line 42, in local_check
self.assertFalse(calibre.run_drc(a.name, tempgds))
File "/home/leepil/OpenRAM-master/compiler/tests/../calibre.py", line
116, in run_drc
debug.error("Unable to retrieve DRC results file. Is calibre set up?",1)
File "/home/leepil/OpenRAM-master/compiler/tests/../debug.py", line 24,
in error
sys.exit(return_value)
SystemExit: 1
This error is commonly shown for about 10 tests.
p.s
(I tried to solve openram in the course of two months after I wanted to
run openram, but I would like to inform you that it was not done. I also
saw the caliber related error I showed as I had already seen. Finally, I
ask for help if I can not solve it at all. Thank you very much.)
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You are receiving this because you commented.
Reply to this email directly, view it on GitHub
<https://github.com/mguthaus/OpenRAM/issues/28#issuecomment-324199582>,
or mute the thread
<https://github.com/notifications/unsubscribe-auth/AL35L59fXbJ8-AafVLI5CPsnV3UAr2Hyks5sa4e2gaJpZM4O5tjk>
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Related Issues (20)
- Unable to read configuration file HOT 3
- openram.py doesn't exist in any tree HOT 1
- Error in SRAM creation with banks HOT 6
- Support for PROBE PDK HOT 4
- ROM dump + replace contents
- ROM >= 8k fails to build HOT 3
- multiports bitcell HOT 1
- Stimuli Generation - sram_func.py or gen_stimuli.py
- Importing a custom GDS file. HOT 7
- Routing error due to high (vertical) density? HOT 1
- No liberty file is created for ROMs HOT 2
- Import custom file HOT 3
- Question: What is the correct allignment in SKY130? Intermediate Pins are not connected to the grid. Likely user mistake. HOT 10
- Errors hidden on default loglevel, but visible on verbose loglevels.
- Support for ASAP7 PDK HOT 1
- Power estimation seems too high HOT 14
- Possible minor error on the documentation related with the ROM usage
- Not generate certain module HOT 1
- Runtime HOT 8
- Adding and Removing Modules and Customizing Module Ports HOT 3
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