Comments (4)
mguthaus
commented on August 16, 2024
Hi Andres,
I just ran this myself and it passed. I am no longer using that Docker and have upgraded to Magic 8.3, so that might be an issue. The error looks like there is a short circuit in the layout.
The "errors" during LVS are expected as we hard code some flatten statements to get rid of LVS symmetry problems. There should be a more elegant way to do this, but we just haven't yet.
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andresag01
commented on August 16, 2024
Hi @mguthaus, you are right! Thanks for the help. I updated the Magic version to 8.3.27 and it works without problems. Perhaps the issue is that the documentation at README.md is out-of-date? I create a PR to address it: #77
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andresag01
commented on August 16, 2024
@mguthaus: Just one follow up question. I am getting the following error when compiling an SRAM with the example config example_config_1rw_1r_scn4m_subm.py with analytical_delay = False (instead of the default True):
LIB: Characterizing...
[characterizer.lib/prepare_tables]: Loads: [ 2.45605 9.8242 39.2968 ]
[characterizer.lib/prepare_tables]: Slews: [0.0125 0.05 0.4 ]
[characterizer.lib/characterize_corners]: Characterizing corners: [('TT', 5.0, 25), ('FF', 5.0, 25), ('SS', 5.0, 25)]
[characterizer.lib/characterize_corners]: Corner: ('TT', 5.0, 25)
[characterizer.lib/characterize_corners]: Writing to /home/andresag/Repos/openram_experiments/tests/sram_rw1_r1_w0/proper/temp/sram_2_16_scn4m_subm_TT_5p0V_25C.lib
[characterizer.delay/find_feasible_period_one_port]: Trying feasible period: 10.0ns on Port 0
[characterizer.delay/find_feasible_period_one_port]: Trying feasible period: 10.0ns on Port 1
[characterizer.delay/find_feasible_period_one_port]: Trying feasible period: 20.0ns on Port 1
[characterizer.delay/find_feasible_period_one_port]: Trying feasible period: 40.0ns on Port 1
[characterizer.delay/find_feasible_period_one_port]: Trying feasible period: 80.0ns on Port 1
[characterizer.delay/find_feasible_period_one_port]: Trying feasible period: 160.0ns on Port 1
[characterizer.delay/find_feasible_period_one_port]: Trying feasible period: 320.0ns on Port 1
[characterizer.delay/find_feasible_period_one_port]: Trying feasible period: 640.0ns on Port 1
[characterizer.delay/find_feasible_period_one_port]: Trying feasible period: 1280.0ns on Port 1
ERROR: file delay.py: line 661: Timed out, could not find a feasible period.
> /home/andresag/Programs/OpenRAM/compiler/debug.py(46)error()
-> assert return_value == 0
(Pdb)
I was initially wondering why openram was taking so long to terminate, so I ran it with debug_level = 1 to get the output above. As you can see, it appears that it failed to characterize and then it ended up on a prompt. Does this work for you? How can I get around the problem?
For reference, the config file is:
word_size = 2
num_words = 16
tech_name = "scn4m_subm"
nominal_corners_only = False
process_corners = ["TT"]
supply_voltages = [5.0]
temperatures = [25]
num_rw_ports = 1
num_r_ports = 1
num_w_ports = 0
route_supplies = True
check_lvsdrc = True
analytical_delay = False
output_path = "temp"
output_name = "sram_{0}_{1}_{2}".format(word_size,
num_words,
tech_name)
debug_level = 1
purge_temp = FalseThe problem also happens when:
num_rw_ports = 0
num_r_ports = 1
num_w_ports = 1
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andresag01
commented on August 16, 2024
The problem was fix with the latest commits in dev. So i will close this issue.
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