Topic: verilog-hdl Goto Github

Some thing interesting about verilog-hdl

👇 Here are 484 public repositories matching this topic...

aklsh / getting-started-with-verilog

verilog-hdl,Verilog modules for beginners

User: aklsh

verilog verilog-hdl verilog-code verilog-snippets open-source

aptx1231 / buaa_co

verilog-hdl,2017级北航计算机学院计算机组成原理课程设计(MIPS CPU)

User: aptx1231

buaa buaa-co mips computer-organization-lab verilog-hdl

arjun-narula / traffic-light-controller-using-verilog

verilog-hdl,the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.

User: arjun-narula

verilog verilog-hdl verilog-project verilog-code verilog-programs verilog-simulator vivado vivado-hls vivado-simulator traffic

ashishrana160796 / verilog-starter-tutorials

verilog-hdl,Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.

User: ashishrana160796

hdl verilog circuit switches iverilog verilog-hdl up-for-grabs beginner-friendly logic-gates practice

aucohl / fault

verilog-hdl,A complete open-source design-for-testing (DFT) Solution

Organization: aucohl

eda dft verilog verilog-hdl vlsi-cad testing jtag scan-chains atpg fault-simulation

b1f6c1c4 / deep-darkfantasy

verilog-hdl,Global Dark Mode for ALL apps on ANY platforms.

User: b1f6c1c4

dark-mode dark-theme dark-mode-toggle fpga verilog verilog-hdl vivado xilinx zynq zynq-7000

ben-marshall / uart

verilog-hdl,A simple implementation of a UART modem in Verilog.

User: ben-marshall

Home Page: https://ben-marshall.github.io/uart/

hardware fpga verilog verilog-hdl uart uart-verilog

bojackchen / digital-flow

verilog-hdl,This is a tutorial on standard digital design flow

User: bojackchen

timing-analysis verilog-hdl synopsys logic-synthesis synthesis

cvonk / fpga_spi

verilog-hdl,Connecting FPGA and Arduino using SPI.

User: cvonk

arduino circuits fpga spi system-verilog verilog-hdl

defparam / higan-verilog

verilog-hdl,This is a higan/Verilator co-simulation example/framework

User: defparam

snes snes-programming emulation fpga verilog verilog-hdl simulation emulator

djzenma / rv32ic-cpu

verilog-hdl,Implementation of the RISC-V 32 bit Integer and Compressed Instructions in Verilog.

User: djzenma

cpu risc-v riscv32 risc verilog rv32i rv32imc riscv32im risc-processor riscv-simulator

dpretet / async_fifo

verilog-hdl,A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

User: dpretet

verilog verification verilog-hdl icarus-verilog fifo fifo-queue fifo-cache synthesis hdl fpga

ekb0412 / 100daysofrtl

verilog-hdl,"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado

User: ekb0412

asic digital-system-design fpga verilog-hdl vlsi-design xilinx-vivado

geraked / verilog-rle

verilog-hdl,Verilog Implementation of Run Length Encoding for RGB Image Compression

User: geraked

verilog fpga ise rle rle-compression-algorithm compression-algorithm verilog-hdl verilog-code image-compression matlab

gowtham1729 / image-processing

verilog-hdl,Image Processing Toolbox in Verilog using Basys3 FPGA

User: gowtham1729

verilog verilog-hdl verilog-project vhdl python3 basys3 basys-board basys fpga pixel

gupta409 / processor-uvm-verification

verilog-hdl,System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment

User: gupta409

uvm systemverilog systemverilog-simulation verilog-hdl verilog processor

halftop / interface-protocol-in-verilog

verilog-hdl,Interface Protocol in Verilog

User: halftop

Home Page: https://halftop.github.io/tag/xaWEXZu1_/

verilog-hdl uart-protocol uart-verilog spi

jed-z / computer-organization-lab

verilog-hdl,中山大学计算机组成原理实验 (2018 秋)：用 Verilog 设计并实现的简易单周期和多周期 CPU

User: jed-z

mips-cpu cpu-designs sysu cpu verilog-hdl

jfoshea / viterbi-decoder-in-verilog

verilog-hdl,An efficient implementation of the Viterbi decoding algorithm in Verilog

User: jfoshea

verilog-hdl viterbi-decoder viterbi-algorithm fpga xilinx

kevinhexin / fpga-bicubic-interpolation

verilog-hdl,use Verilog HDL implemente bicubic interpolation in FPGA

User: kevinhexin

fpga bicubic-interpolation verilog-hdl video-scaler

lightcode / 8bit-computer

verilog-hdl,A simple 8-bit computer build in Verilog.

User: lightcode

verilog-hdl

matejgomboc / verilog-i2s-transciever

verilog-hdl,I2S transciever implemented in Verilog HDL

User: matejgomboc

verilog-hdl i2s-audio python

maxs-well / ad7606-driver-verilog

verilog-hdl,AD7606 driver verilog

User: maxs-well

ad7606 adi adc verilog verilog-hdl driver

maxs-well / ethernet-design-verilog

verilog-hdl,Gigabit Ethernet UDP communication driver

User: maxs-well

ethernet communication driver verilog verilog-hdl rtl8211 udp

maxs-well / lms-sound-filtering-by-verilog

verilog-hdl,LMS sound filtering by Verilog

User: maxs-well

lms sound-filtering verilog verilog-hdl

metr0jw / spiking-neural-network-on-fpga

verilog-hdl,Leaky Integrate and Fire (LIF) model implementation for FPGA

User: metr0jw

computational-neuroscience neuromorphic-computing snn spiking-neural-network spiking-neural-networks verilog verilog-hdl leaky-integrate-and-fire-model leaky-integrate-and-fire-neuron lif-model

michaelehab / aes-verilog

verilog-hdl,Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL

User: michaelehab

aes aes-128 aes-192 aes-256 aes-decryption aes-encryption cryptography fpga fpga-board fpga-soc

michaelvll / riscv_cpu

verilog-hdl,A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL

User: michaelvll

verilog-hdl risc-v

mihir8181 / veriloghdl-codes

verilog-hdl,Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.

User: mihir8181

verilog verilog-project verilog-code verilog-programs verilog-hdl n-bit-alu counter fsm moore-machine-code mealy-machine-code

mongrelgem / verilog-adders

verilog-hdl,Implementing Different Adder Structures in Verilog

User: mongrelgem

adder verilog verilog-project verilog-hdl hardware-designs

mshr-h / vscode-verilog-hdl-support

verilog-hdl,HDL support for VS Code

User: mshr-h

verilog-hdl vscode systemverilog verilog language-server-client iverilog modelsim verilator ctags vivado

neelkshah / mips-processor

verilog-hdl,5-stage pipelined 32-bit MIPS microprocessor in Verilog

User: neelkshah

bits-pilani computer-architecture computer-organisation computer-organization microprocessor microprocessors mips-architecture mips-instructions mips-processor verilog verilog-components verilog-hdl verilog-programs verilog-project verilog-simulator verilog-snippets

nngen / nngen

verilog-hdl,NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network

Organization: nngen

neural-network high-level-synthesis hardware veriloggen pyverilog deep-learning compiler verilog-hdl python onnx

pendkeomkar / spi

verilog-hdl,Title : Communication Bridge between I2C and SPI Platform : RTL Coding (Verilog/System Verilog/VHDL) Duration : 1 Month Description : Both SPI and I2C are robust, stable communication protocols that are widely used in today's complex systems.The I2C bus has a minimum pin count requirement and therefore a smaller footprint on the board. The SPI bus provides a synchronized serial link with performance in MHz range.The project implements the bridge between the two protocols and serves as an interface between these two which allow direct communication and a solution to reduce development time and cost for complex embedded systems.

User: pendkeomkar

verilog uvm verilog-hdl verilog-programs verilog-project verification verification-methodologies verification-codes verification-component spi

pyhdi / pyverilog

verilog-hdl,Python-based Hardware Design Processing Toolkit for Verilog HDL

Organization: pyhdi

verilog-hdl hardware compiler parser dataflow-analyzer control-flow-analyzer code-generator python

pyhdi / veriloggen

verilog-hdl,Veriloggen: A Mixed-Paradigm Hardware Construction Framework

Organization: pyhdi

verilog-hdl python pyverilog high-level-synthesis hardware hardware-construction-language compiler

rusys / verugent

verilog-hdl,Verilog generation tool written in Rust

Organization: rusys

rust verilog-hdl verilog-verugent

sarthak268 / embedded_logic_and_design

verilog-hdl,This repository contains all labs done as a part of the Embedded Logic and Design course.

User: sarthak268

verilog verilog-hdl verilog-programs verilog-project embedded-systems embedded-logic logic-circuit logic-programming embedded-c c vhdl vhdl-code zedboard xilinx xilinx-vivado xilinx-fpga xilinx-sdk arm vivado pmod

sdasgup3 / parallel-processor-design

verilog-hdl,Super scalar Processor design

User: sdasgup3

verilog-hdl processor verilog processor-architecture processor-simulator instruction-set-architecture superscalar pipeline-processor pipeline-cpu assembler

snbk001 / verilog-design-examples

verilog-hdl,Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous FIFO, 8x8 Sequential Multiplier

User: snbk001

verilog testbenches verilog-design verilog-code verilog-hdl verilog-programs verilog-project self-checking

spider-tronix / vlsi

verilog-hdl,RISC V core implementation using Verilog.

Organization: spider-tronix

risc verilog-hdl computer-architecture cpu risc-v fpga processor

sudhamshu091 / 32-verilog-mini-projects

verilog-hdl,Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM

User: sudhamshu091

verilog verilog-project miniproject verilog-hdl

thedatabusdotio / fpga-ml-accelerator

verilog-hdl,This repository hosts the code for an FPGA based accelerator for convolutional neural networks

User: thedatabusdotio

Home Page: https://thedatabus.io

fpga hardware digital-design verilog-hdl vhdl asic verification

thesupercd / 8bit_microcomputer_verilog

verilog-hdl,This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This project was developed as a Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.

User: thesupercd

verilog verilog-hdl verilog-project verilog-code iverilog 8bit ben-eater ben-eaters-cpu