ben-marshall Goto Github PK

aes-sboxes

Somewhere to put different implementations of the AES SBox

ann-playground

Code I develop while learning about Artificial Neural Networks

awesome-open-hardware-verification

A List of Free and Open Source Hardware Verification Tools and Frameworks

awesome-semiconductor-startups

List of awesome semiconductor startups

ben-marshall.github.io

My personal website, such as it is.

configuration-structure

RISC-V Configuration Structure

croyde-riscv

A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.

cssbristol.github.io

Source code for the UoB Computer Science Society web portal

doxygen-themes

A collection of the various Doxygen Theme customisations I have created and used.

latex-boilerplate

A simple latex boilerplate with makefile for common commands.

microcoder

Define custom assembly-like instructions and use them to write programs which are transpiled into synthesisable Verilog code.

riscv-arch-test

riscv-bitmanip

Working draft of the proposed RISC-V Bitmanipulation extension

riscv-isa-sim

Spike, a RISC-V ISA Simulator

riscv-multi-cycle

WIP - A multi-cycle implementation of the RISCV rv32ui architecture. *unverified, use PicoRV32 instead!*

riscv-opcodes

RISC-V Opcodes

riscv-tests

riscv-zkt-list

Zkt "safe list": extension attests that the machine has data-independent execution time for these instructions

sail-riscv

Sail RISC-V model

sat-solver

A simple combinatorial boolean sat solver based on the AC-3 Algorithm

silver

SILVER - Statistical Independence and Leakage Verification

tim

A small CPU core complete with compiler and ISA specification. Eventually....

uart

A simple implementation of a UART modem in Verilog.

vanilla-riscv

Vanilla RISC-V core, implementing RV32IMC

verilog-doc

A basic documentation generator for Verilog, similar to Doxygen.

verilog-dot

A simple dot file / graph generator for Verilog syntax trees.

verilog-parser

A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.

verilog-probe

A very small and simple debug probe designed to be very easy to interface with and be usable via SPI, JTAG and UART.

verilog-vcd-parser

A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.