Topic: high-level-synthesis Goto Github
Some thing interesting about high-level-synthesis
Some thing interesting about high-level-synthesis
high-level-synthesis,:dart: soap - Structural Optimisation of Arithmetic Programs
User: admk
high-level-synthesis,This repo has codes for hardware accelerator design for CNNs using high level synthesis from Altera.
User: amohant4
high-level-synthesis,High-Level Synthesis with Partial Evaluation
Organization: anydsl
high-level-synthesis,AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper accepted to ICCAD2023)!
Organization: arc-research-lab
high-level-synthesis,CHARM: Composing Heterogeneous Accelerators on Versal ACAP Architecture
Organization: arc-research-lab
high-level-synthesis,A Vivado HLS Command Line Helper Tool
User: benjmarshall
high-level-synthesis,DaCH: dataflow cache for high-level synthesis.
User: brigio345
high-level-synthesis,Intermediate Language (IL) for Hardware Accelerator Generators
Organization: calyxir
Home Page: https://calyxir.org
high-level-synthesis,FPGA Accelerator for CNN using Vivado HLS
User: changwoolee
high-level-synthesis,Allo: A Programming Model for Composable Accelerator Design
Organization: cornell-zhang
Home Page: https://cornell-zhang.github.io/allo
high-level-synthesis,A graph linear algebra overlay
Organization: cornell-zhang
high-level-synthesis,HeteroCL-MLIR dialect for accelerator design
Organization: cornell-zhang
Home Page: https://cornell-zhang.github.io/heterocl/index.html
high-level-synthesis,HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing
Organization: cornell-zhang
Home Page: https://cornell-zhang.github.io/heterocl/
high-level-synthesis,High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
Organization: cornell-zhang
high-level-synthesis,Time-sensitive affine types for predictable hardware generation
Organization: cucapra
Home Page: https://capra.cs.cornell.edu/dahlia
high-level-synthesis,A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
User: definelicht
high-level-synthesis,A crypto accelerator written for HLS to an FPGA that actually makes it slower than running it on your computer
User: doctor3w
high-level-synthesis,High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.
User: federicoserafini
high-level-synthesis,PandA-bambu public repository
Organization: ferrandi
high-level-synthesis,XLS: Accelerated HW Synthesis
Organization: google
Home Page: http://google.github.io/xls/
high-level-synthesis,A Compiler for the Popr Language
User: hackerfoo
Home Page: https://popr.dev
high-level-synthesis,Tutorials on HLS Design
Organization: hlslibs
high-level-synthesis,DUTH RISC V Microprocessor for High Level Synthesis
Organization: ic-lab-duth
high-level-synthesis,Fast Floating Point Operators for High Level Synthesis
Organization: ic-lab-duth
high-level-synthesis,Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis
Organization: ic-lab-duth
high-level-synthesis,HLS for Networks-on-Chip
Organization: ic-lab-duth
high-level-synthesis,CHO is a benchmark suite for OpenCL FPGA Accelerators
User: it302
Home Page: http://it302.github.io/cho
high-level-synthesis,A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
User: juliankemmerer
Home Page: https://github.com/JulianKemmerer/PipelineC/wiki
high-level-synthesis,Bream is a subset/dialect of Scheme that is compiled to run on an alternative platform. More details & initial sources will follow soon.
User: karttu
high-level-synthesis,Monte Carlo Methods applied to the Black-Scholes financial market model
User: max2ma
Home Page: https://github.com/KitAway/BlackScholes_MonteCarlo
high-level-synthesis,
User: max2ma
high-level-synthesis,
User: max2ma
high-level-synthesis,
User: ngiambla
high-level-synthesis,NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network
Organization: nngen
high-level-synthesis,Near-storage compute aware file system and FPGA operator pipelines.
Organization: osmhpi
Home Page: https://metalfs.github.io
high-level-synthesis,FPGA Cryptography for High-Level Synthesis
User: petrsocha
high-level-synthesis,Polyphony is Python based High-Level Synthesis compiler.
Organization: polyphony-dev
high-level-synthesis,Veriloggen: A Mixed-Paradigm Hardware Construction Framework
Organization: pyhdi
high-level-synthesis,[FPGA 2023] FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs
User: ripperj
high-level-synthesis,FPGA acceleration of arbitrary precision floating point computations.
Organization: spcl
high-level-synthesis,DaCe - Data Centric Parallel Programming
Organization: spcl
Home Page: http://dace.is/fast
high-level-synthesis,Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
Organization: spcl
high-level-synthesis,Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".
Organization: spcl
high-level-synthesis,
Organization: spcl
high-level-synthesis,HeteroGen: transpiling C to heterogeneous HLS code with automated test generation and program repair (ASPLOS 2022)
Organization: ucla-seal
high-level-synthesis,Convert C files into Verilog
User: wvangansbeke
high-level-synthesis,A formally verified high-level synthesis tool based on CompCert and written in Coq.
User: ymherklotz
Home Page: https://vericert.ymhg.org
high-level-synthesis,HLS code for Network on Chip (NoC)
User: zhipengzhaocmu
Home Page: https://research.ece.cmu.edu/~coram/doku.php?id=connect-hls
high-level-synthesis,Implement High-Performance Karatsuba Multiplier in High-Level Synthesis (HLS) for FPGA Based on Recursive Template
User: zslwyuan
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