Topic: asic Goto Github
Some thing interesting about asic
Some thing interesting about asic
asic,IC implementation of Systolic Array for TPU
User: abdelazeem201
asic,Cryptocurrency ASIC mining hardware monitor using a simple web interface
User: anselal
asic,Haskell to VHDL/Verilog/SystemVerilog compiler
Organization: clash-lang
Home Page: https://clash-lang.org/
asic,Allo: A Programming Model for Composable Accelerator Design
Organization: cornell-zhang
Home Page: https://cornell-zhang.github.io/allo
asic,A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
User: dpretet
asic,An AXI4 crossbar implementation in SystemVerilog
User: dpretet
asic,Digital Signature Service : creation, extension and validation of advanced electronic signatures
Organization: esig
Home Page: https://ec.europa.eu/digital-building-blocks/wikis/display/DIGITAL/Digital+Signature+Service+-++DSS
asic,Control and Status Register map generator for HDL projects
User: esynr3z
Home Page: https://corsair.readthedocs.io
asic,Reverse-engineered schematics for DMG-CPU-B
User: furrtek
asic,Custom chips reverse-engineered from silicon
User: furrtek
asic,PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).
Organization: google
Home Page: https://gf180mcu-pdk.rtfd.io
asic,
Organization: google
Home Page: https://sky90fd-pdk.rtfd.io
asic,Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
Organization: google
Home Page: https://skywater-pdk.rtfd.io
asic,Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
Organization: juniper
asic,KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi
Organization: kasirga-kizil
asic,8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.
User: lakshmi-sathi
asic,Hive OS client for ASICs
Organization: minershive
Home Page: https://hiveos.farm
asic,The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Organization: openhwgroup
Home Page: https://docs.openhwgroup.org/projects/cva6-user-manual/
asic,The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
Organization: pulp-platform
asic,AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Organization: pulp-platform
asic,A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
Organization: pulp-platform
asic,A 256-RISC-V-core system with low-latency access into shared L1 memory.
Organization: pulp-platform
asic,Tiny ASIC implementation for "The Era of 1-bit LLMs All Large Language Models are in 1.58 Bits" matrix multiplication unit
User: rejunity
asic,RISC-V Cores, SoC platforms and SoCs
Organization: riscvarchive
Home Page: https://riscv.org/risc-v-cores/
asic,Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
User: secworks
asic,Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
Organization: sld-columbia
asic,🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
User: stnolting
asic,SystemRDL 2.0 language compiler front-end
Organization: systemrdl
Home Page: http://systemrdl-compiler.readthedocs.io
asic,Open source machine learning accelerators
Organization: tensil-ai
Home Page: https://www.tensil.ai
asic,OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Organization: the-openroad-project
Home Page: https://openlane.readthedocs.io/
asic,This repository hosts the code for an FPGA based accelerator for convolutional neural networks
User: thedatabusdotio
Home Page: https://thedatabus.io
asic,GDS3D is an application that can interpret so called IC layouts and render them in 3D. The program accepts standard GDSII files as input data. Along with the layout file, it requires a so called process definition file which contains the 3D parameters of the process being used. These files combined allow the program to create a 3D representation of the layout, where the user has full, real time control over the camera position and angle, much like in a 3D video game. An other repo (https://github.com/skuep/GDS3D) as the same source and add few improvement like compression with server/client process. This release add two major feature with are assembly and export 3D model for GMSH. Assembly: this mean it’s possible to merge multi GDS (with different technologies) I also try to improve net highlight.
User: trilomix
asic,Awesome ASIC design verification
User: troyguo
asic,32-bit Superscalar RISC-V CPU
User: ultraembedded
asic,Various HDL (Verilog) IP Cores
User: ultraembedded
asic,RISC-V CPU Core (RV32IM)
User: ultraembedded
asic,A seamless python to Cadence Virtuoso Skill interface
Organization: unihd-cag
Home Page: https://unihd-cag.github.io/skillbridge/
asic,A simplified and standardized interface for Bitcoin ASICs.
User: upstreamdata
Home Page: https://docs.pyasic.org
asic,IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
Organization: vlsi-eda
Home Page: https://tu-dresden.de/ing/informatik/ti/vlsi
asic,VUnit is a unit testing framework for VHDL/SystemVerilog
Organization: vunit
Home Page: http://vunit.github.io/
asic, collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning
User: zssloth
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