SLAC Ultimate RTL Framework
Setup for large filesystems on github. git-lfs
used for all binary files (example: .dcp)
$ git lfs install
An Introduction to SURF Presentation
A huge VHDL library for FPGA development
License: Other
SLAC Ultimate RTL Framework
Setup for large filesystems on github. git-lfs
used for all binary files (example: .dcp)
$ git lfs install
An Introduction to SURF Presentation
I was looking at SlvDelayFifo, deciding whether to use it, and I noticed something in the code that troubled me.
if (fifoReadoutTime <= r.timeNow) then
I believe the "<" test will cause the fifo to advance unexpectedly when the fifoReadoutTime signal wraps around and the r.timeNow signal has not yet wrapped. That causes the output to be asserted earlier than intended. An "=" test would be better, but then a reset is needed whenever the delay signal is altered.
Lefthand signal to be exchanged with rigthhand in assignment
Hi!
I have been looking into the AxiStreamRepeater.vhd and I need to use it in a project.
How can I add the surf library to my project?
I see in the code:
library surf;
use surf.StdRtlPkg.all;
use surf.AxiStreamPkg.all;
I cloned the repo and run setup.py but did not know how to continue.
I have been successfully building my code with Vivado 2019.1. I updated my surf library to tag v2.34.0 and the build no longer works. I eventually traced it to file base/ram/ruckus.tcl
which was changed to only include the source files under base/ram/xilinx
if the Vivado version is > 2019.1
. This should be >= 2019.1
to include Vivado 2019.1. I made that change locally and the builds works again.
I have been using SURF and Ruckus for an on-going project (for High-Energy Physics applications).
I need to generate more detailed post-PAR reports in order to see the utilization of GT transceivers.
Vivado supports a Tcl command named report_utilization , how can i add it to the Ruckus system so that it is executed automatically ?
thanks,
I tried to test the AxiLiteCrossbar block with Xilinx AXI VIP.
I got a protocol violation at the first transaction I tried. This was before I was able to fully configure the address decoder or the address of the transaction, so the transaction is a decoder error.
Xilinx SIP reported:
Fatal: AXI4_ERRS_BRESP_AW: A slave must not give a write response before the write address. Spec: section A3.3.1 and figure A3-7.
Time: 560 ns Iteration: 1 Process: /axisim_tb/DUT/axi_vip_mst[0]/inst/IF/PC/Always3445_217 Scope: axisim_tb.DUT.\axi_vip_mst[0] .inst.IF.PC.arm_amba4_pc_msg_err File: /tools/Xilinx/Vivado/2020.1/data/xilinx_vip/hdl/axi_vip_axi4pc.sv Line: 727
According to IHI0022E_amba_axi_and_ace_protocol_spec.pdf, BVALID should wait for both AW and W channel transactions to finish before beeing aserted, see figure A3-7 on page A3-44.
The instance generics were:
int unsigned NUM_SLAVE_G = 4,
int unsigned NUM_MASTER_G = 1,
constant MASTERS_CONFIG_G : AxiLiteCrossbarMasterConfigArray(0 to 0) := (
0 => (baseAddr => X"00000000", addrBits => 32, connectivity => X"FFFF")
);
I was focused on the multiplexer, therefore a single master port.
I probably misconfigured the design somehow, since I did not expect a decoder error.
I did not review the RTL to see if a misconfiguration could have caused this protocol violation.
E-VHDL-1077: ../../submodules/surf/devices/Ti/adc32rf45/rtl/adc32rf45.vhd(150): expression has 25 elements ; expected 24
I-VHDL-1156: ../../submodules/surf/devices/Ti/adc32rf45/rtl/adc32rf45.vhd(25): netlist '\adc32rf45(spi_sclk_period_g=1.0E-006)(rtl)' remains a black box, due to errors in its contents
E-VHDL-1077: ../../submodules/surf/devices/Ti/adc32rf45/rtl/adc32rf45.vhd(150): expression has 25 elements ; expected 24
AxiDualPortRam distributed latency issue when setting READ_LATENCY_G = 2. Actual latency ends up being 1, probably because there is no DOB_REG
https://github.com/slaclab/surf/blob/master/axi/axi-lite/rtl/AxiDualPortRam.vhd#L189-L190
Hi:
I am trying to rebuild a Caui4Core project using the ruckus.tcl inside the directory, and i am using the Vivado 2019.1.3 on Win10 systems, when the source the tcl file, it shows something error below:
ERROR: [Runs 36-335] 'D:/Ref_design/surf/surf/ethernet/Caui4Core/gtyUltraScale+/ip/Caui4GtyIpCore156MHz.dcp' is not a valid design checkpoint
so, did i do something wrong, how can i build a example project?
Thanks a lot.
If using FifoMux with RD_DATA_WIDTH_G < WR_DATA_WIDTH_G
, it works if rd_en
is held high until the FIFO is empty. However, if rd_en
goes low when rdR.count = (RD_SIZE_C-1)
, the below line will cause fifo_rd_en
, which controls wr_en for the FIFO, to actually go high and stay high for every clock. This may empty out the contents of the FIFO depending on when rd_en
goes high again to advance rdR.count
. Since rd_en
is low, the state machine controlling rd_en
will likely not be able to make use of this firehose of data coming out of the FIFO and the data will certainly not get demuxed.
After scratching my head over this and adding a ChipScope ILA, I finally found the offending line to be:
surf/base/fifo/rtl/FifoMux.vhd
Line 225 in 0484417
FifoMux works as expected with new data only being presented on dout
after rd_en
is a 1 if this line gets changed to:
fifo_rd_en <= rd_en and toSl(rdR.count = (RD_SIZE_C-1));
We had some issues with the Gtx7Core module, where clock correction was not occurring and eventually led to elastic buffer under- or overflows. It turns out that the culprit was the following:
RXCHBONDSLAVE => toSl(RX_CHAN_BOND_MASTER_G = false),
I would have thought that the status of this bit would not matter at all when RXCHANBONDEN was also tied low via:
RXCHBONDEN => toSl(RX_CHAN_BOND_EN_G),
But as it turns out, somehow RXCHBONDSLAVE being '1' was suppressing all clock corrections. The fix we implemented was:
RXCHBONDSLAVE => toSl(RX_CHAN_BOND_EN_G = true and RX_CHAN_BOND_MASTER_G = false),
We only have seen this issue in the Gtx7Core, having not tried it in any others yet, but I suspect a similar issue may occur in the GTP and GTH modules. Also, we had RX_CHAN_BOND_MASTER_G
set to false, so RXCHBONDMASTER was then set to '0'. Probably a similar change should be added to RXCHBONDMASTER to check whether RX_CHAN_BOND_EN_G is true, but under this condition (RXCHBONDMASTER = '1', but RXCHBONDEN = '0') there doesn't seem to be a conflict with clock correction, at least in simulation.
The following fails to synthesize:
U_AXI_RAM : entity surf.AxiDualPortRam
generic map (
TPD_G => TPD_G,
SYNTH_MODE_G => "xpm",
MEMORY_TYPE_G => "distributed",
READ_LATENCY_G => 2,
AXI_WR_EN_G => true,
SYS_WR_EN_G => false,
COMMON_CLK_G => true,
ADDR_WIDTH_G => 10,
DATA_WIDTH_G => 10)
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