bogdanvuk / pygears Goto Github PK

Modules such as ccat.v, cast_dout.v, sieve.v are using continous assignment on output reg signals. eg.

module abc( output reg dout_valid);   // should be output wire
    assign dout_valid = 10;
endmodule

Yosys reports warning:

Warning: reg '\dout_s' is assigned in a continuous assignment at ...

Vivado reports error:

[Synth 8-1852] concurrent assignment to a non-net dout_s is not permitted ["..."]

In the following code, the variable PYPY is used but is not defined. This raises an error on cpython versions < 3.7.

A user ran into this issue on stack overflow https://stackoverflow.com/q/63994839/5666087

Await clk() command might cause sim/cosim differences. Might be specific to the case I encountered it but on the other hand it might not. Take extra care when using this command!

https://github.com/Risto97/pygears_issues/blob/master/data_dly/run_test.py
Verilator fails to compile data_dly gear because of missing dreg.sv.

I see 3 ways for resolving this.
-Append dreg verilog module in data_dly.sv file (simplest).

-Generate dreg gear modules in loop like in data_dly2(), this is not optimal because of multiple dreg.sv files generated. Also python fails with recursion error for more than 1000 instances (maybe a seperate issue).

-Try implement it in hls.

GTK wave code is not shown as it should be

pygears-tools-install pyenv python pygears fails
cat ~/.pygears/tools/pygears/_install/pip.log

Collecting git+git://github.com/bogdanvuk/pygears.git
  Cloning git://github.com/bogdanvuk/pygears.git to /tmp/pip-req-build-fnq_s69e
  Running command git clone -q git://github.com/bogdanvuk/pygears.git /tmp/pip-req-build-fnq_s69e
  fatal: remote error:
    The unauthenticated git protocol on port 9418 is no longer supported.
  Please see https://github.blog/2021-09-01-improving-git-protocol-security-github/ for more information.
ERROR: Command errored out with exit status 128: git clone -q git://github.com/bogdanvuk/pygears.git /tmp/pip-req-build-fnq_s69e Check the logs for full command output.

Await clk() could cause a gear to never have the done flag raised. This flag is needed to check simulation finalization. This is expected behavior but take care as it could cause simulations that run endlessly.

I'm just getting started with pygears. Noticed that some links in the README are broken.

images/echo.png
images/echo_plot.png
images/echo_vcd.png

Current implementation of "rom" gear has a fixed 1 cycle delay latency support.

pygears > pygears > lib > rom.py

An improvement would be defining a configurable parameter which could select '0' cycle delay rom implementation

This test is failing:
https://github.com/Risto97/pygears_issues/blob/master/timeout_test/run_sim.py

Presentation on the website is not mobile-friendly, this should be fixed in the future.

Since we are no longer pygears.org instead of documentation we are using doc.pygears.org
Some of examples here are having bad links: https://pygears.org/echo.html#echo-examples

When running cosim simulation and enabling pytest debugging messages pygears has multiple issues

• To reproduce:

• have the cosim enabled
• run pytest with "--log-cli-level=DEBUG" option

• issues

1. libs "astpretty" and "networkx" not installed by default by pygears -> as a workaround should be installed manually
2. the simulation blocks and never finishes