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backup-openbilibili-go-common

2019年4-22日-bilibili-干杯站后端源码（原包删除前最后一版170M）

chisel-template

clash-verge

A Clash GUI based on tauri. Supports Windows, macOS and Linux.

dgn

DGN Code

e200_opensource

The Ultra-Low Power RISC Core

fuxi

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

helloflask

Hello, Flask!

istyle-verilog-formatter

Open source implementation of a Verilog formatter

nocgen

NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers

nocmodel

NoCmodel is a Python module for Network-on-Chip modeling, with add-ons for simulation (functional or RTL) and code generation.

openpiton

The OpenPiton Platform

policy-gnn

pt-rs

pygears

HW Design: A Functional Approach

pytorch_dgn

The pytorch implementation of DGN on grid world and Starcraft

pyverilator

Python wrapper for verilator model

rcore-tutorial-v3

Let's write an OS which can run on RISC-V in Rust from scratch!

react-resume-site

木及简历，一款markdown的在线简历工具。

remote-desktop

A toy remote desktop implemented by python

replace-23b

This project is derived from RePlAce(https://github.com/The-OpenROAD-Project/RePlAce)

riscv-assembler

RISC-V Assembly code assembler package for Python.

shadowsocks-rust

A Rust port of shadowsocks

systolic-array

A DSL for Systolic Arrays

tclwrapper

Python wrapper to interact with TCL command line interfaces

terminus

A riscv isa simulator in rust.

tinvrv2

tray_rust

A toy ray tracer in Rust