aucohl / fault Goto Github PK

A complete open-source design-for-testing (DFT) Solution

License: Apache License 2.0

Swift 80.43% Dockerfile 1.05% Python 1.22% Shell 2.14% Tcl 0.06% SourcePawn 14.97% Nix 0.13%

eda dft verilog verilog-hdl vlsi-cad testing jtag scan-chains atpg fault-simulation

fault's Introduction

🧪 Fault

Fault is a complete open source design for testing (DFT) Solution that includes automatic test pattern generation for netlists, scan chain stitching, synthesis scripts and a number of other convenience features.

Quick Setup/Walkthrough

You may refer to the wiki for quick setup instructions (and a small walkthrough!) if you're into that.

Detailed installation instructions

If you don't feel like using (or can't use) Docker, you can try Installing.md for full installation instructions.

Running

Subcommands

synth

Synth is a synthesis script included with Fault that generates a netlist. You may elect to use your own synthesis script, but this is provided for your convenience.

To run it, fault synth --top <your-top-module> --liberty <your-liberty-file> <your-file>.

For more options, you can invoke fault synth --help.

cut

fault cut <your-netlist>

This exposes the D-flipflops as ports for use with the main script.

For more options, you can invoke fault cut --help.

main

fault --clock <clockName> --cellModel <your-cell-models> <your-file>.

A set of assumptions are made about the input file:

It is a netlist
It is flattened (there is only one module with no submodules)
The flipflops have been cut away and replaced with outputs and inputs.

Generated test vectors are printed to stdout by default, but you can use -o <file> (or simply redirect the output).

For more options, you can invoke fault --help.

chain

fault chain --liberty <your-liberty-file> --clock <clockName> --reset <resetName> <--activeLow> <your-file>.

Chain is another synthesis script that links registers together for scan insertion. It takes all the assumptions made in the main program but the last, and one more:

All instantiated D flipflops start with "DFF".

A note about the liberty file in use in this step is that we recommend a modified liberty file that keeps only a buffer, an and gate, and a multiplexer (and an inverter if necessary), as abc tends to overthink multiplexers.

Chain will output information about the scan chain embedded in the output netlist as /* FAULT METADATA: '<json>' */ after the boilerplate. This metadata includes things like port names, the DFF count and the order of the registers in the scan chain.

You can have Chain automagically verify its generated scanchain-- see the help for more options, but the gist of it is -v <your-cell-model>.

For more options, you can invoke fault chain --help.

asm

fault asm <test vector json> <chained netlist>, in any order, will assemble a .bin file for use with $readmemb.

For more options, you can invoke fault asm --help.

compact

fault compact <test vector json>

This performs static compaction on the generated test vectors by reducing the test vectors count while keeping the same coverage.

For more options, you can invoke fault compact --help.

tap

fault tap --liberty <liberty> [--cellModel <cell model>] --clock <clockName> --reset <resetName> <chained netlist>

Tap adds JTAG interface to a chained netlist. Currently, two scan chains are supported: the boundary cell scan chain and the internal registers chain. Tap supports the IEEE 1149.1 four mandatory: Extest, Bypass, Sample, and Preload. Also, it has been extended to support ScanIn (4'b 0100) instruction to select the internal register chain.

A cell model can optionally be passed to verify the tap.

For more information on the supported instructions, check the example testbench.

For more options, you can invoke fault tap --help.

Copyright & Licensing

SOFTWARE INCLUDED WITH FAULT DISTRIBUTIONS, I.E. ATALANTA AND PODEM, WHILE FREE TO DISTRIBUTE, ARE PROPRIETARY, AND MAY NOT BE USED FOR COMMERCIAL PURPOSES.

References

Z. Navabi, Digital System Test and Testable Design : Using Hdl Models and Architectures. 2010;2011;. DOI: 10.1007/978-1-4419-7548-5. Book
Shinya Takamaeda-Yamazaki: Pyverilog: A Python-based Hardware Design Processing Toolkit for Verilog HDL, 11th International Symposium on Applied Reconfigurable Computing (ARC 2015) (Poster), Lecture Notes in Computer Science, Vol.9040/2015, pp.451-460, April 2015. Paper

Publication(s)

M. Abdelatty, M. Gaber, M. Shalan, "Fault: Open Source EDA’s Missing DFT Toolchain," IEEE Design & Test Magazine. April 2021. Paper
Mohamed Gaber, Manar Abdelatty, and Mohamed Shalan, "Fault, an Open Source DFT Toolchain," Article No.13, Workshop on Open-Source EDA Technology (WOSET), 2019. Paper

fault's People

Contributors

Stargazers

Watchers

fault's Issues

Swift not found

I was installing Fault and I had already installed Swift in my Ubuntu 20.04 yet while installing Fault I faced an error SWIFT not found.

Docker image issue

Hello,

when I type in the terminal, the below shown

docker run -tiv pwd:pwd -w pwd --rm cloudv/fault:latest fault -V

I am getting the following error

docker: Error response from daemon: OCI runtime create failed: container_linux.go:345: starting container process caused "process_linux.go:299: copying bootstrap data to pipe caused "write init-p: broken pipe"": unknown.

Missing external test set example file s27.v.tv.json

Hi,
The external test vector example file s27.v.tv.json ( PATH :RTL/ISCAS_89/s27.v.tv.json) is missing.
Would appreciate if the file would be availabl

e as I want to use external test set for my research purposes.
The link is broken.

Thanks

Request to give installaion walk-through

Dear,

I humbly request you to give step-by-step clean walk-through tutorial as to how to install. There is lot of confusion in the current shown approach.

Please, it is a request.

Humble request to ensure this as well

https://github.com/Cloud-V/Fault/blob/75dd9eafb5c5f05c1c34f3636a571875de1fa191/Dockerfile#L35

I am getting the following error

root@zakir-virtual-machine:/share# cp . /share/Fault
cp: -r not specified; omitting directory '.'

Fault Coverage issue

In FAULT, the fault coverage of a test vector includes the faults in those extra lines which have been obtained after synthesis and cutting of flipflops. But, if we want to find out the fault coverage in terms of the original verlilog file, then how to do that

Create a super simple test

Modify Tests/FaultTests/FaultTests.swift to run a simple test for the entire Fault suite

Error message "Option --clock is required." when run Fault Simulation

I reference below link
https://github.com/AUCOHL/Fault/wiki/Usage

in Fault Simulations, I found error log as below

(base) tonyho@ubuntu5:~/workspace/fault/Fault$ fault -c Tech/osu035/osu035_stdcells.v -v 100 -r 50 -m 95 --ceiling 1000 Netlists/s27.netlist.v.cut.v 
Option --clock is required.
Invoke fault --help for more info.

after try it, I add "--clock CK" then pass as below.
I think document need update.

(base) tonyho@ubuntu5:~/workspace/fault/Fault$ fault -c Tech/osu035/osu035_stdcells.v -v 100 -r 50 -m 95 --ceiling 1000 Netlists/s27.netlist.v.cut.v --clock CK
Generating LALR tables
WARNING: 183 shift/reduce conflicts
Processing module s27…
Found 48 fault sites in 12 gates and 15 ports.
Performing simulations…
Skipped 4 duplicate generated test vectors.
Minimum coverage not met (81.25%/95.0%,) incrementing to 150…
Skipped 4 duplicate generated test vectors.
Minimum coverage not met (81.25%/95.0%,) incrementing to 200…
Skipped 11 duplicate generated test vectors.
Minimum coverage not met (81.25%/95.0%,) incrementing to 250…
Skipped 10 duplicate generated test vectors.
Minimum coverage not met (81.25%/95.0%,) incrementing to 300…
Skipped 11 duplicate generated test vectors.
Minimum coverage not met (81.25%/95.0%,) incrementing to 350…
Skipped 9 duplicate generated test vectors.
Minimum coverage not met (81.25%/95.0%,) incrementing to 400…
Skipped 17 duplicate generated test vectors.
Minimum coverage not met (81.25%/95.0%,) incrementing to 450…
Skipped 14 duplicate generated test vectors.
Minimum coverage not met (81.25%/95.0%,) incrementing to 500…
Skipped 15 duplicate generated test vectors.
Minimum coverage not met (81.25%/95.0%,) incrementing to 550…
Skipped 17 duplicate generated test vectors.
Minimum coverage not met (81.25%/95.0%,) incrementing to 600…
Skipped 16 duplicate generated test vectors.
Minimum coverage not met (81.25%/95.0%,) incrementing to 650…
Skipped 26 duplicate generated test vectors.
Minimum coverage not met (81.25%/95.0%,) incrementing to 700…
Skipped 30 duplicate generated test vectors.
Minimum coverage not met (81.25%/95.0%,) incrementing to 750…
Skipped 27 duplicate generated test vectors.
Minimum coverage not met (81.25%/95.0%,) incrementing to 800…
Skipped 28 duplicate generated test vectors.
Minimum coverage not met (81.25%/95.0%,) incrementing to 850…
Skipped 28 duplicate generated test vectors.
Minimum coverage not met (81.25%/95.0%,) incrementing to 900…
Skipped 26 duplicate generated test vectors.
Minimum coverage not met (81.25%/95.0%,) incrementing to 950…
Skipped 27 duplicate generated test vectors.
Minimum coverage not met (81.25%/95.0%,) incrementing to 1000…
Skipped 38 duplicate generated test vectors.
Hit ceiling. Settling for current coverage.
Time elapsed: 6.14s.
Simulations concluded: Coverage 81.25%

README: main takes --clock

fault main takes --clock which README ignores

Scan chain Verification failed

Hi,
While running fault chain command I bumped into an error. Please refer image.

I generated TV with default options. The prompt displays "Scan chain verification failed". I'm confused, which program is being referenced here that requires clock and reset? The netlist generated using yosys contained reset and clock signals.
The reset in my design is synchronous(and is the only reset signal).
Even with all these errors, .chained file is created in my netlist folder. I'm able to run tap asm command and check the created .bin files.
I encountered similar issue while running fault tap command. .jtag file was created but the prompt displayed "Tap port verification failed".

Also, I'm curious to know what would have been the output if both these steps verified successfully.

Regards,
Piyush

Pyverilog not found

I was trying, but ending up with this following error. Please help

fault synth -t ha --liberty /home/zakir/bin/FaultInstall/Tech/osu035/osu035_stdcells.lib ./ha.v
Fatal error: 'try!' expression unexpectedly raised an error: Python exception: No module named 'pyverilog': file /share/Fault/.build/checkouts/PythonKit/PythonKit/Python.swift, line 683
Current stack trace:
0 libswiftCore.so 0x00007fa999ecaec0 swift_reportError + 50
1 libswiftCore.so 0x00007fa999f3bf60 _swift_stdlib_reportFatalErrorInFile + 115
2 libswiftCore.so 0x00007fa999e5ff0e + 3514126
3 libswiftCore.so 0x00007fa999e60087 + 3514503
4 libswiftCore.so 0x00007fa999c5582d + 1374253
5 libswiftCore.so 0x00007fa999e36e68 + 3346024
6 libswiftCore.so 0x00007fa999c8d7a1 + 1603489
7 fault 0x00005590de3f00df + 631007
8 fault 0x00005590de3c17b2 + 440242
9 fault 0x00005590de3afaf0 + 367344
10 libc.so.6 0x00007fa997d50ab0 __libc_start_main + 231
11 fault 0x00005590de3695ba + 79290
Illegal instruction (core dumped)

Support SKY130

Self-explanatory. We don't need to mess around with OSU or Nangate now that we have an honest to goodness open source PDK.

That, and Fault is supposed to be integrated into OpenLane someday. So.

Check hierarchy for first run

Hierarchy is not checked for first run, so RTLs that are invalid are ignored.

We need to ignore it for the second run as it cannot import the scl models, but for the first run there is no such requirement.

Add thread pools

Currently, we leave it up to DispatchQueue to decide how many threads are in use. This may not be efficient for high TV increments.

Query - Transition Faults

Is it possible to do Transition faults testing using Fault?

Request for references

could you please send the paper of 11th reference to me? my email: [email protected].

Error while running spm design with Sky130A library

MAINTAINER EDIT: ISSUE REOPENED BECAUSE OF THIS COMMENT: #13 (comment)

I am trying to run spm with Fault. Synthesis and Cut commands are successful but when I try to run
fault -c Tech/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v -v 100 -r 50 -m 95 --ceiling 1000 Netlists/spm.netlist.v.cut.v
Which actually uses sky130_fd_sc_hd.v file, the following error appears.

Generating LALR tables
WARNING: 183 shift/reduce conflicts
Processing module CSADD…
Found 25 fault sites in 6 gates and 5 ports.
Performing simulations…
Skipped 84 duplicate generated test vectors.
./Tech/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:40410: syntax error./Tech/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:40410: syntax error
./Tech/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:40410: error: invalid module item.

./Tech/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:40410: error: invalid module item.
./Tech/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:40410: syntax error
./Tech/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:40410: error: invalid module item.
./Tech/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:40410: syntax error
./Tech/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:40410: error: invalid module item.

I am unable to find the issue.

Change macro behavior to connect to multiplexed clock instead of leaving clock untouched

Title

Create a simple tutorial in the wiki

Create a basic guide showing how to use Fault on a design from A->Z.

JTAG Command causing an error

I tried to run the JTAG port insertion command but following error caused exiting the process. Is it a bug or something missing at my end?

WARNING: 183 shift/reduce conflicts
Creating top module\u2026
Stitching tap port...
Syntax error
Fatal error: 'try!' expression unexpectedly raised an error: Python exception: :8: before: library
Traceback:
  File "/usr/local/lib/python3.6/dist-packages/pyverilog/vparser/parser.py", line 2296, in parse
    ast = codeparser.parse()
  File "/usr/local/lib/python3.6/dist-packages/pyverilog/vparser/parser.py", line 2274, in parse
    ast = self.parser.parse(text, debug=debug)
  File "/usr/local/lib/python3.6/dist-packages/pyverilog/vparser/parser.py", line 77, in parse
    return self.parser.parse(text, lexer=self.lexer, debug=debug)
  File "/usr/local/lib/python3.6/dist-packages/pyverilog/vparser/ply/yacc.py", line 265, in parse
    return self.parseopt_notrack(input,lexer,debug,tracking,tokenfunc)
  File "/usr/local/lib/python3.6/dist-packages/pyverilog/vparser/ply/yacc.py", line 1047, in parseopt_notrack
    tok = self.errorfunc(errtoken)
  File "/usr/local/lib/python3.6/dist-packages/pyverilog/vparser/parser.py", line 2246, in p_error
    self._coord(p.lineno))
  File "/usr/local/lib/python3.6/dist-packages/pyverilog/vparser/plyparser.py", line 55, in _parse_error
    raise ParseError("%s: %s" % (coord, msg))
: file /share/Fault/.build/checkouts/PythonKit/PythonKit/Python.swift, line 602
Current stack trace:
0    libswiftCore.so                    0x00007f1d53268ea0 swift_reportError + 50
1    libswiftCore.so                    0x00007f1d532d9f40 _swift_stdlib_reportFatalErrorInFile + 115
2    libswiftCore.so                    0x00007f1d531fdeee <unavailable> + 3514094
3    libswiftCore.so                    0x00007f1d531fe067 <unavailable> + 3514471
4    libswiftCore.so                    0x00007f1d52ff37cd <unavailable> + 1374157
5    libswiftCore.so                    0x00007f1d531d4e48 <unavailable> + 3345992
6    libswiftCore.so                    0x00007f1d5302b741 <unavailable> + 1603393
7    fault                              0x00005644228eb09a <unavailable> + 1650842
8    fault                              0x000056442285e336 <unavailable> + 1073974
9    fault                              0x000056442286bcb3 <unavailable> + 1129651
10   fault                              0x000056442286bea1 <unavailable> + 1130145
11   fault                              0x0000564422882fd0 <unavailable> + 1224656
12   fault                              0x000056442286b943 <unavailable> + 1128771
13   libc.so.6                          0x00007f1d510edab0 __libc_start_main + 231
14   fault                              0x000056442277760a <unavailable> + 128522
Illegal instruction (core dumped)`````

File seems to be broken

In Detailed installation instructions section, INSTALLING.md hyperlink seem to be broken.

synth only creates a netlist

README says:

Synth is a synthesis script included with Fault that generates both a netlist and a cut-away version.

But synth only creates a netlist in Netlists/

Fault is not accepting Synopysis Design Compiler generated netlist

I am trying to run FAULT on Swerve el-2 design. I have DC synthesized netlist which is mapped on Sky 130 A library. When I try to run the cut command following error appears.
Command:
fault cut -d sky130_fd_sc_hd__dfrtp_1 Netlists/netlist.v

Output:

Generating LALR tables
WARNING: 183 shift/reduce conflicts
Fatal error: 'try!' expression unexpectedly raised an error: Python exception:  line:23: before: "."
Traceback:
  File "/usr/local/lib/python3.6/dist-packages/pyverilog/vparser/parser.py", line 2338, in parse
    ast = codeparser.parse()
  File "/usr/local/lib/python3.6/dist-packages/pyverilog/vparser/parser.py", line 2316, in parse
    ast = self.parser.parse(text, debug=debug)
  File "/usr/local/lib/python3.6/dist-packages/pyverilog/vparser/parser.py", line 77, in parse
    return self.parser.parse(text, lexer=self.lexer, debug=debug)
  File "/usr/local/lib/python3.6/dist-packages/ply/yacc.py", line 333, in parse
    return self.parseopt_notrack(input, lexer, debug, tracking, tokenfunc)
  File "/usr/local/lib/python3.6/dist-packages/ply/yacc.py", line 1201, in parseopt_notrack
    tok = call_errorfunc(self.errorfunc, errtoken, self)
  File "/usr/local/lib/python3.6/dist-packages/ply/yacc.py", line 192, in call_errorfunc
    r = errorfunc(token)
  File "/usr/local/lib/python3.6/dist-packages/pyverilog/vparser/parser.py", line 2268, in p_error
    self._raise_error(p)
  File "/usr/local/lib/python3.6/dist-packages/pyverilog/vparser/parser.py", line 2279, in _raise_error
    raise ParseError("%s: %s" % (coord, msg))
: file PythonKit/Python.swift, line 602
Current stack trace:
0    libswiftCore.so                    0x00007fb46ba62990 swift_reportError + 50
1    libswiftCore.so                    0x00007fb46bad6260 _swift_stdlib_reportFatalErrorInFile + 115
2    libswiftCore.so                    0x00007fb46b7bb925 <unavailable> + 1399077
3    libswiftCore.so                    0x00007fb46b7bb567 <unavailable> + 1398119
4    libswiftCore.so                    0x00007fb46b7bbb02 <unavailable> + 1399554
5    libswiftCore.so                    0x00007fb46b7b9fa0 _assertionFailure(_:_:file:line:flags:) + 517
6    libswiftCore.so                    0x00007fb46b807859 <unavailable> + 1710169
7    fault                              0x000056190d8e926a <unavailable> + 1466986
8    fault                              0x000056190d859f06 <unavailable> + 880390
9    fault                              0x000056190d876413 <unavailable> + 996371
10   fault                              0x000056190d876511 <unavailable> + 996625
11   fault                              0x000056190d883853 <unavailable> + 1050707
12   fault                              0x000056190d8762be <unavailable> + 996030
13   libc.so.6                          0x00007fb469c96b10 __libc_start_main + 231
14   fault                              0x000056190d7a37fa <unavailable> + 133114
Illegal instruction (core dumped)

I have attached the netlist herewith.

netlist.txt

Compilation on `aarch64` failing

Compiling Fault on Ubuntu 22.04 on amd64 works, but the same installation on arm64 fails. The following code line leads to a hangup:

let python3 = "python3 -V".shOutput()

Fault simulation with external test pattern set ?

Could you please help how to do Fault simulation with the external test pattern set.

can you please ensure these steps are correct?

https://github.com/Cloud-V/Fault/blob/75dd9eafb5c5f05c1c34f3636a571875de1fa191/Dockerfile#L26

Help Option is Broken

Hi,
I'm trying to install Fault on Windows Subsystem for Linux (WSL2). I installed prerequisites for the software and all of them are working fine. However, when I try to install Fault in my system, it gives me an error. Find the image below-

I don't understand what the error is about.

Note: I did not install Atalanta or PODEM as they were optional and thought to use the software's pattern generation

Please help.

Regards,
Piyush

Open source test pattern generation

Atalanta is not open-source (research use only). It seems that there is no open source ATPG solution around.
I've been developing one, quaigh, which is mostly compatible with Atalanta (.bench files and similar .test files) with a lot of additional stuff (limited .blif support, Lut support, ...).

Would you be interested if I try and integrate it with Fault?

Build fails on Ubuntu 22.04

Version 71b3588 fails the build process with the following error:

#0 13.20 HEAD is now at 71b3588 venvs + Update Documentation (#36)
#0 14.06 install.swift:50:19: error: 'ProcessInfo' initializer is inaccessible due to 'internal' protection level
#0 14.06 let processInfo = ProcessInfo()
#0 14.06                   ^
#0 14.06 Foundation.ProcessInfo (internal):3:23: note: 'init()' declared here
#0 14.06     override internal init()

@donn Can you please take a look?

Issue at Fault simulation step

hi @donn

i am just trying out the usage steps given in wiki, but i am facing this issue as shown in the image, any idea how to fix it and move ahead?

i am using ubuntu 20.04.5

and have installed all packages too.

please do help me resolve this error.

thank you!

Migrate to Python3

Currently Swift 5.2 is in use. It is better to migrate to Python3.

While Installing Fault using INSTALL_DIR=/usr/bin swift install.swift

While Installing Fault using INSTALL_DIR=/usr/bin swift install.swift
I am getting the shown below

root@zakir-virtual-machine:/share/Fault# INSTALL_DIR=/usr/bin swift install.swift
usage: swift [--version] [--help] [--os-help] [--snet] [--verbose]
[--debug] [--info] [--quiet] [--auth <auth_url>]
[--auth-version <auth_version> |
--os-identity-api-version <auth_version> ]
[--user ]
[--key <api_key>] [--retries <num_retries>]
[--os-username ] [--os-password ]
[--os-user-id ]
[--os-user-domain-id ]
[--os-user-domain-name ]
[--os-tenant-id ]
[--os-tenant-name ]
[--os-project-id ]
[--os-project-name ]
[--os-project-domain-id ]
[--os-project-domain-name ]
[--os-auth-url ] [--os-auth-token ]
[--os-storage-url ] [--os-region-name ]
[--os-service-type ]
[--os-endpoint-type ]
[--os-cacert ] [--insecure]
[--os-cert ]
[--os-key ]
[--no-ssl-compression]
[--help] []

Command-line interface to the OpenStack Swift API.

Positional arguments:

delete Delete a container or objects within a container.
download Download objects from containers.
list Lists the containers for the account or the objects
for a container.
post Updates meta information for the account, container,
or object; creates containers if not present.
copy Copies object, optionally adds meta
stat Displays information for the account, container,
or object.
upload Uploads files or directories to the given container.
capabilities List cluster capabilities.
tempurl Create a temporary URL.
auth Display auth related environment variables.

Examples:
swift download --help

swift -A https://api.example.com/v1.0
-U user -K api_key stat -v

swift --os-auth-url https://api.example.com/v2.0
--os-tenant-name tenant
--os-username user --os-password password list

swift --os-auth-url https://api.example.com/v3 --auth-version 3
--os-project-name project1 --os-project-domain-name domain1
--os-username user --os-user-domain-name domain1
--os-password password list

swift --os-auth-url https://api.example.com/v3 --auth-version 3
--os-project-id 0123456789abcdef0123456789abcdef
--os-user-id abcdef0123456789abcdef0123456789
--os-password password list

swift --os-auth-token 6ee5eb33efad4e45ab46806eac010566
--os-storage-url https://10.1.5.2:8080/v1/AUTH_ced809b6a4baea7aeab61a
list

swift list --lh
no such command: install.swift

compilation terminated

when I am using the following command , I am getting compilation terminated

swift iverilog_build.swift

parse.cc:465:10: fatal error: parse.hh: No such file or directory
465 | #include "parse.hh"
| ^~~~~~~~~~
compilation terminated.
make: *** [Makefile:245: parse.o] Error 1

Number of inputs in the json doesn't equal to the scan-chain registers

I am facing a mismatch in the number of inputs and the scan chain registers when running this command:

$ fault asm ./Netlists/SPM.netlist.v.cut.v.tv.json ./Netlists/SPM.netlist.v.cut.v.chained.v

Output:

[Error]: number of inputs in the json 67 doesn't equal to the scan-chain registers 66.
Make sure you ignored clock & reset signals in the TV generation.

Invalid Test Vector File

For circuit s27 , I am writing my own test vector file as given in s27.v.tv.json

But will running the tool, it is showing invalid test vector file. @cmarqu can look into the issue??

Add support for special patterns

Add ability to generate special patterns unlikely to be generated by pseudo-RNG, such as:

Alternating 0s and 1s
Half-and-half
All 0s
Walking block of 1s

AND ALL OF THEIR COMPLEMENTS

Display of Test vectors generated

In JSON file the test vectors are generated. How will I understand the sequence of the test vectors i.e. which value is corresponding to which signal. and the fault coverage of each test vector

Fault switches not working

@donn
I am facing issues with fault, after completion of the installation procedure, when I am trying to get version using fault --version/-V
It's showing me the help menu every time, not only that, only subcommand are working like

fault synth --top xyz -l xyz.lib xyz.v > its working
fault cut xyz.netlist.v > its also working but when I am trying to run fault --cellModel xyz.v filename its not working instead showing help menu every time.

Working with Combinational Designs

Hi,

I was running the design c17.v in Benchmarks/ISCAS_85. However, while generating TV, the command requires me to add clock as well and obviously a combinational circuit does not have clock.

Verilog Code:

My question: Is it possible to generate TV and find faults for pure combinational designs?