Comments (12)
donn
commented on May 20, 2024
Alright, in the future we'd intensely appreciate uploading the offending file(s) because the file in question is actually generated by open_pdks. It is not a "standard" file.
The issue will be tracked in RTimothyEdwards/open_pdks#87. This may be an issue with any of IcarusVerilog, open_pdks or the Skywater PDK, but ultimately not Fault.
from fault.
mahmoodulhassan-lm
commented on May 20, 2024
Alright, in the future we'd intensely appreciate uploading the offending file(s) because the file in question is actually generated by open_pdks. It is not a "standard" file.
The issue will be tracked in RTimothyEdwards/open_pdks#87. This may be an issue with any of IcarusVerilog, open_pdks or the Skywater PDK, but ultimately not Fault.
@donn
Thanks for the clarification.
from fault.
mahmoodulhassan-lm
commented on May 20, 2024
@donn
I prefixed '1' with \ on line 40410 in the file sky130_fd_sc_hd.v and included primitives.v file. Now following message is being shown.
fault -c Tech/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v -v 100 -r 50 -m 95 --ceiling 100 Netlists/spm.netlist.v.cut.v
Generating LALR tables
WARNING: 183 shift/reduce conflicts
Processing module CSADD…
Found 25 fault sites in 6 gates and 5 ports.
Performing simulations…
Skipped 84 duplicate generated test vectors.
[Warning]: golden output contains x or z.
[Warning]: golden output contains x or z.
[Warning]: golden output contains x or z.
[Warning]: golden output contains x or z.
[Warning]: golden output contains x or z.
[Warning]: golden output contains x or z.
[Warning]: golden output contains x or z.
[Warning]: golden output contains x or z.
[Warning]: golden output contains x or z.
[Warning]: golden output contains x or z.
[Warning]: golden output contains x or z.
[Warning]: golden output contains x or z.
[Warning]: golden output contains x or z.
[Warning]: golden output contains x or z.
[Warning]: golden output contains x or z.
[Warning]: golden output contains x or z.
Hit ceiling. Settling for current coverage.
Time elapsed: 3.61s.
Simulations concluded: Coverage 0.0%
I have attached sky130_fd_sc_hd.txt and primitives.txt for reference
sky130_fd_sc_hd.txt
from fault.
donn
commented on May 20, 2024
Thanks for the report, we'll investigate
from fault.
Manarabdelaty
commented on May 20, 2024
@mahmoodulhassan-lm
The following macros have to be defined to be able to run the simulations with sky130
`define FUNCTIONAL
`define UNIT_DELAY #0
Can you verify that these macros were set ? You can add them to sky130_fd_sc_hd.v
EDIT: The UNIT_DELAY macro must be set to #0 so that Fault's generated testbenches work out of the box. Setting the macro otherwise will add extra-delay to the scan-chain serial output
from fault.
mahmoodulhassan-lm
commented on May 20, 2024
@Manarabdelaty when I entered both of the above definitions in sky130_fd_sc_hd.v , the following error popped up.
fault -c Tech/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v -v 100 -r 50 -m 95 --ceiling 100 Netlists/spm.netlist.v.cut.v
Generating LALR tables
WARNING: 183 shift/reduce conflicts
Processing module CSADD…
Found 25 fault sites in 6 gates and 5 ports.
Performing simulations…
Skipped 84 duplicate generated test vectors.
./Tech/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:19754: syntax error
I give up.
./Tech/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:19754: syntax error
I give up.
./Tech/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:19754: syntax error
I give up.
./Tech/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:19754: syntax error
I give up.
from fault.
Manarabdelaty
commented on May 20, 2024
I think it is because the lpflow_bleeder cells in the verilog views have syntax errors in the current version. I commented them out in the file you posted and was able to successfully pass it to Iverilog without syntax errors.
from fault.
mahmoodulhassan-lm
commented on May 20, 2024
@Manarabdelaty
Please look into the output now.
fault -c Tech/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v -v 100 -r 50 -m 95 --ceiling 1000 Netlists/spm.netlist.v.cut.v
Generating LALR tables
WARNING: 183 shift/reduce conflicts
Processing module CSADD…
Found 25 fault sites in 6 gates and 5 ports.
Performing simulations…
Skipped 84 duplicate generated test vectors.
[Warning]: golden output contains x or z.
[Warning]: golden output contains x or z.
[Warning]: golden output contains x or z.
[Warning]: golden output contains x or z.
[Warning]: golden output contains x or z.
[Warning]: golden output contains x or z.
[Warning]: golden output contains x or z.
[Warning]: golden output contains x or z.
Minimum coverage not met (4.0%/95.0%,) incrementing to 150…
Skipped 50 duplicate generated test vectors.
Minimum coverage not met (4.0%/95.0%,) incrementing to 200…
Skipped 50 duplicate generated test vectors.
Minimum coverage not met (4.0%/95.0%,) incrementing to 250…
Skipped 50 duplicate generated test vectors.
Minimum coverage not met (4.0%/95.0%,) incrementing to 300…
Skipped 50 duplicate generated test vectors.
Minimum coverage not met (4.0%/95.0%,) incrementing to 350…
Skipped 50 duplicate generated test vectors.
Minimum coverage not met (4.0%/95.0%,) incrementing to 400…
Skipped 50 duplicate generated test vectors.
Minimum coverage not met (4.0%/95.0%,) incrementing to 450…
Skipped 50 duplicate generated test vectors.
Minimum coverage not met (4.0%/95.0%,) incrementing to 500…
Skipped 50 duplicate generated test vectors.
Minimum coverage not met (4.0%/95.0%,) incrementing to 550…
Skipped 50 duplicate generated test vectors.
Minimum coverage not met (4.0%/95.0%,) incrementing to 600…
Skipped 50 duplicate generated test vectors.
Minimum coverage not met (4.0%/95.0%,) incrementing to 650…
Skipped 50 duplicate generated test vectors.
Minimum coverage not met (4.0%/95.0%,) incrementing to 700…
Skipped 50 duplicate generated test vectors.
Minimum coverage not met (4.0%/95.0%,) incrementing to 750…
Skipped 50 duplicate generated test vectors.
Minimum coverage not met (4.0%/95.0%,) incrementing to 800…
Skipped 50 duplicate generated test vectors.
Minimum coverage not met (4.0%/95.0%,) incrementing to 850…
Skipped 50 duplicate generated test vectors.
Minimum coverage not met (4.0%/95.0%,) incrementing to 900…
Skipped 50 duplicate generated test vectors.
Minimum coverage not met (4.0%/95.0%,) incrementing to 950…
Skipped 50 duplicate generated test vectors.
Minimum coverage not met (4.0%/95.0%,) incrementing to 1000…
Skipped 50 duplicate generated test vectors.
Hit ceiling. Settling for current coverage.
Time elapsed: 2.67s.
Simulations concluded: Coverage 4.0%
One more thing I would like to mention that I am using sky130_fd_sc_hd__tt_100C_1v80.lib as a lib file.
from fault.
Manarabdelaty
commented on May 20, 2024
Can you post spm.netlist.v.cut.v ?
from fault.
mahmoodulhassan-lm
commented on May 20, 2024
Can you post spm.netlist.v.cut.v ?
Please find both .netlist and netlist.cut.
spm.netlist.v.cut.txt
spm.netlist.txt
from fault.
mahmoodulhassan-lm
commented on May 20, 2024
There is an issue with chain insertion commands as well.
fault chain -l Tech/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib -c Tech/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v --clock clk --reset rst Netlists/spm.netlist.v
Generating LALR tables
WARNING: 183 shift/reduce conflicts
Chaining internal flip-flops…
Internal scan chain successfuly constructed. Length: 0
Creating and chaining boundary flip-flops…
Generating LALR tables
WARNING: 183 shift/reduce conflicts
Boundary scan cells successfuly chained. Length: 3
Total scan-chain length: 3
Resynthesizing with yosys…
Verifying scan chain integrity…
Generating LALR tables
WARNING: 183 shift/reduce conflicts
done
Scan chain verification failed.
・Ensure that clock and reset signals, if they exist are passed as such to the program.
・Ensure that the reset is active high- pass --activeLow for activeLow.
・Ensure that D flip-flop cell name starts with ["DFFSR", "DFFPOSX1", "DFFNEGX1"].
・Ensure that there are no other asynchronous resets anywhere in the circuit.
Done.
In sky130_fd_sc_hd.v, cells definitions are different from Osu35. For example, flipflops names start with sky130_fd_sc_hd__udp_dff$PR_pp$PG$N or sky130_fd_sc_hd__dfrtp_1, etc.
Please do correct me if I am understanding it wrong.
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Manarabdelaty
commented on May 20, 2024
-
I noticed that the synthesized netlist only has the CSADD module. To generate synthesized netlist with the SPM as top module, you need to specify the top module name using the -t option as follows
fault synth -l /ef/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_100C_1v65.lib -t SPM -o spm.synthesis.v spm.v
(You will need to replace the liberty file path with your own path) -
The low coverage you are exhibiting in the simulation is because the cut netlist wasn't generated correctly. The cut option should remove all flip-flop cells from the design. If you examined the netlist, you will see that the netlist still has flip-flop cells (I think we need to add a warning message for failing to detect any flip-flop cells) To specify the flip-flop cell name, you can use -d option as follows:
fault cut -d sky130_fd_sc_hd__dfrtp_1 spm.synthesis.v
(You will need to make sure that the synthesized netlist indeed has flip-flop cells namedsky130_fd_sc_hd__dfrtp_1; also note that this name will vary from design to design)
I have attached the synthesized and the cut netlists I generated using above commands for your reference.
spm.synthesis.txt
spm.synthesis.v.cut.txt
from fault.
Related Issues (20)
- Working with Combinational Designs HOT 7
- File seems to be broken
- Request for references HOT 1
- Number of inputs in the json doesn't equal to the scan-chain registers HOT 1
- Migrate to Python3 HOT 1
- Display of Test vectors generated
- Missing external test set example file s27.v.tv.json HOT 6
- compilation terminated HOT 1
- synth only creates a netlist
- README: main takes --clock
- Invalid Test Vector File HOT 1
- Fault Coverage issue HOT 1
- Issue at Fault simulation step HOT 1
- Build fails on Ubuntu 22.04 HOT 1
- Error message "Option --clock is required." when run Fault Simulation HOT 1
- Change macro behavior to connect to multiplexed clock instead of leaving clock untouched
- Add thread pools
- Add support for special patterns
- Open source test pattern generation HOT 1
- Compilation on `aarch64` failing
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