armleo Goto Github PK

arduino-generic-xvc

Generic Arduino Xilinx XVC server

armenian-phonetic

Armenian phonetic keyboard layout for Mac OSX. Հայերեն ֆոնետիկ ստեղնաշար Mac OSX-ի համար։

armleo_gpio

HighSpeed LVCMOS IO Cell IP for sky130; GPLv3 licensed. Use at your own risk. MPW5 Tapeout: https://github.com/armleo/armleo_gpio_mpw5

armleo_gpio_mpw5

A test chip tapeout for MPW5 (confirmed); HighSpeed LVCMOS IO Cell IP for sky130: https://github.com/armleo/armleo_gpio

armleocpu

ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set

armleocpu_clint

CLINT implementation for ArmleoCPU

armleocpu_plic

DEPRECATED! RISC-V PLIC Compilant AXI4-Lite controller.

armleocpu_toolset

Docker Toolset for ArmleoCPU

armleopc_nexusboards

ArmleoPC project's boards

armleopc_qemu_old

QEMU Custom build with ArmleoPC support

armleopc_sky130

Skywater 130nm Tapeout using Open-MPW

armleoscript

Own Scipting Language

async_mem_example

Construct async read memory from block memory in FPGA

axi4_article_habr

axi4litetosimpleconverter

DEPRECATED! This module converts AXI4 Lite to simple interface

caravel_fpu

ddr3_sstl_fork

DDR3 SSTL Test analog caravel user project

ebaz4205

A 5$ Xilinx ZYNQ development board.

ebaz4205-projectfiles

Vivado and PetaLinux projects for Zynq EBAZ4205 Board

expect_at_not_showing

See: https://github.com/chipsalliance/chisel3/issues/1939

firrtl_backend_confusing_error_reproduction

ggx

How To Retarget the GNU Toolchain in 21 Patches

iverilog_seg_fault_0

letthepartygoon

node-base

Node basi app

node-bf

Brainfuck to node.js compiler and runner

openhabr

Open alternative forum for everybody

openlane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

openofdm

Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.

ponylink

A single-wire bi-directional chip-to-chip interface for FPGAs