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Hello there 👋

My name is Suhas Kudlur Viswanath and I am an avid enthusiast of open Instruction Set Architectures like RISC-V. I mainly develop RTL for processors using the RISC-V ISA, some more RTL for data-centric architectures like PIM and some sw on the side to aid with the above.

Suhas Kudlur Viswanath's Projects

ai-aes icon ai-aes

This is a submission for Efabless AI Generated Design Contest.

avst_adder icon avst_adder

Example setup for UVM driven Icarus Verilog Simulation

cayde icon cayde

cayde is 32-bit RISC-V core written in SystemVerilog

ccn-lab icon ccn-lab

This repository contains the files required for the Computer Communication Networks course for 5th semester.

cft icon cft

Circuit Fault Tester: This tool will process a netlist and the faults in the netlist.

control_systems_matlab icon control_systems_matlab

This repo consists of all the MATLAB code for the Control Systems course of the 4th Semester ECE department.

diablo icon diablo

diablo is an Out-Of-Order 64-bit RISC-V processor.

digital-com-matlab icon digital-com-matlab

This repository contains MATLAB files for the Digital Communication course of 4th semester of ECE.

dsp_lab icon dsp_lab

This repository consists of all the MATLAB programs of the Principles of Digital Signal Processing Laboratory of 4th semester of ECE department.

eleventy-duo icon eleventy-duo

Eleventy Duo is a minimal and beautiful Eleventy theme for personal blogs.

euvm-ws icon euvm-ws

Files from the eUVM Workshop by InCore Semiconductors.

gegit icon gegit

gegit -> Getting your personal Git repositories from your terminal made easy

gravity icon gravity

gravity is a p2p file transfer tool.

intel-fpga icon intel-fpga

This repo contains SV and Sycl code for the FPGA Academy using Intel FPGAs on the oneAPI platform.

litex icon litex

Build your hardware, easily!

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