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vscode-verilog-hdl-support's Introduction

HDL support for VS Code

HDL support for VS Code with Syntax Highlighting, Snippets, Linting, Formatting and much more!

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sample

Installation

Install it from VS Code Marketplace or Open VSX Registry.

Features

  • Syntax Highlighting
    • Verilog-HDL
    • SystemVerilog
    • Bluespec SystemVerilog
    • VHDL
    • Vivado UCF constraints
    • Synopsys Design Constraints
    • Verilog Filelists (dot-F files)
    • Tcl
  • Simple Snippets
  • Linting support from:
    • Icarus Verilog - iverilog
    • Modelsim - modelsim
    • Verilator - verilator
    • Vivado Logical Simulation - xvlog
    • [Experimental] Slang - slang
  • Linting support
    • Bluespec SystemVerilog
  • Ctags Integration
    • Autocomplete
    • Document Symbols Outline
    • Hover over variable declaration
    • Go to Definition & Peek Definition
    • Module Instantiation
  • [Experimental] Language Server support from:
  • [Experimental] Formatting support from:

Usage Instructions

  • All linters expect the executable binary ( iverilog , verilator ...) to be present in the PATH environment variable, unless otherwise specified.
  • While using `include directives, the path to the files should be relative to the workspace directory, unlessrunAtFileLocation is enabled (not supported by all linters)

Ctags Integration

This extension uses the tags created using Ctags to provide many of its features. It is recommended to use Universal Ctags as it supports SystemVerilog also, compared to Exuberant Ctags and other older versions. The tags are stored in memory and not as separate files.

Currently the integrated feature supports only tags in the currently opened file, not tags in other files. However, you can use other independent Ctags extensions to find definitions from any file.

For example Ctags Companion works well with this extension by adding the following settings on .vscode/settings.json in your workspace.

{
    "ctags-companion.command": "ctags -R --fields=+nKz -f .vscode/.tags --langmap=SystemVerilog:+.v -R rtl /opt/uvm-1.2/src",
    "ctags-companion.readtagsEnabled": true,
}

It searches for definitions not only in the workspace, but also in files outside the workspace (ex. /opt/uvm-1.2/src in the example above). It also supports the readtags command included in Universal Ctags, allowing for fast searches from large workspaces.

Installation of Universal Ctags

  • Windows - Daily builds are available at ctags-win32
  • Linux - Installation instructions are here
  • macOS - Install through Homebrew from here

Add the installation path of Ctags binary in your PATH environment variable or mention it in verilog.ctags.path setting.

Commands

  • Rerun lint tool

    Choose a lint tool from the list and run it manually. Useful if the code was changed by an external script or version control system.

  • Instantiate Module

    Choose a module present in your workspace to instantiate it in the current file.

Language Servers (Experimental)

We currently support the following Language Servers and enabled for Verilog-HDL, SystemVerilog and VHDL. You can enable multiple Language Servers at the same time. It might be pretty unstable because it's currently in the experimental support. If you encounter any problems even if it's not related to this feature, deleting all the config may solve the problem.

Language Server Verilog-HDL SystemVerilog VHDL
svls not supported enabled not supported
veridian not supported enabled not supported
HDL Checker enabled enabled enabled
verible-verilog-ls enabled enabled not supported
rust_hdl not supported not supported enabled

Formatting (Experimental)

We currently support Verilog-HDL file formatting with the following formatters.

You can format the Verilog-HDL file by typing Ctrl-Shift-p, then select Format Document. Entire file formatting is supported. Selected range formatting is not supported yet. All the settings for formatting is under verilog.formatting namespace.

Configuration Settings

Use the following settings to configure the extension to your needs.

  • verilog.linting.linter (Default: none )

    Choose the linter for you. Possible values are

    • iverilog
    • modelsim
    • slang
    • verilator
    • xvlog
    • none
  • verilog.linting.iverilog.arguments (Default: nothing)

    Add custom arguments to Icarus Verilog for linting, like -Wall . The argument -t null will be added by the linter automatically.

  • verilog.linting.iverilog.includePath (Default: nothing)

    A list of directory paths to use while Icarus Verilog linting. All the paths are passed as arguments -I <directory_path>. Paths can be specified either an absolute or a relate to the workspace directory.

  • verilog.linting.iverilog.runAtFileLocation (Default: false )

    By default, the linter will be run at the workspace directory. Enable this option to run at the file location. If enabled, ` include directives should contain file paths relative to the current file.

  • verilog.linting.modelsim.arguments (Default: nothing)

    Add custom arguments to Modelsim for linting.

  • verilog.linting.modelsim.work (Default: nothing)

    Add custom work library to Modelsim for linting.

  • verilog.linting.slang.arguments (Default: nothing)

    Add Slang arguments here (like macros). They will be added to Slang while linting (The command "-I=" will be added by the linter by default).

  • verilog.linting.slang.includePath (Default: nothing)

    A list of directory paths to use while Slang linting.

  • verilog.linting.slang.runAtFileLocation (Default: false )

    If enabled, Slang will be run at the file location for linting. Else it will be run at workspace folder. Disabled by default.

  • verilog.linting.slang.useWSL (Default: false )

    Run verilator under WSL. Paths generated automatically by the extension (the path to the Verilog file as well as the auto-generated document folder for -I ) are translated to WSL paths using the wslpath program. Any other paths you specify in verilog.linting.includePath.arguments

  • verilog.linting.verilator.arguments (Default: nothing)

    Add custom arguments to Verilator for linting, like -Wall . The argument --lint-only -I<document folder> will be added by the linter automatically.

  • verilog.linting.verilator.includePath (Default: nothing)

    A list of directory paths to use while Verilator linting. All the paths are passed as arguments -I<directory_path>. Paths can be specified either an absolute or a relate to the workspace directory.

  • verilog.linting.verilator.runAtFileLocation (Default: false )

    By default, the linter will be run at the workspace directory. Enable this option to run at the file location. If enabled, ` include directives should contain file paths relative to the current file.

  • verilog.linting.verilator.useWSL (Default: false )

    Run verilator under WSL (use apg-get install verilator to install). Paths generated automatically by the extension (the path to the Verilog file as well as the auto-generated document folder for -I ) are translated to WSL paths using the wslpath program. Any other paths you specify in verilog.linting.verilator.arguments

    must be manually converted.

  • verilog.linting.xvlog.arguments (Default: nothing)

    Add custom arguments to Xilinx xvlog for linting, like -Wall . The argument --nolog will be added by the linter automatically.

  • verilog.linting.xvlog.includePath (Default: nothing)

    A list of directory paths to use while Xilinx xvlog linting. All the paths are passed as arguments -i <directory_path>. Paths can be specified either an absolute or a relate to the workspace directory.

  • verilog.ctags.path (Default: ctags )

    Path to your installation of Ctags if it isn't already present in your PATH environment variable.

  • verilog.languageServer.svls.enabled (Default: false)

    [Experimental] Enable svls Language Server for SystemVerilog.

  • verilog.languageServer.svls.path (Default: svls)

    [Experimental] A path to the svls Language Server binary.

  • verilog.languageServer.veridian.enabled (Default: false)

    [Experimental] Enable veridian Language Server for SystemVerilog.

  • verilog.languageServer.veridian.path (Default: veridian)

    [Experimental] A path to the veridian Language Server binary.

  • verilog.languageServer.hdlChecker.enabled (Default: false)

    [Experimental] Enable HDL Checker Language Server for Verilog-HDL, SystemVerilog, and VHDL.

  • verilog.languageServer.hdlChecker.path (Default: hdl_checker)

    [Experimental] A path to the HDL Checker Language Server binary.

  • verilog.languageServer.veribleVerilogLs.enabled (Default: false)

    [Experimental] Enable verible-verilog-ls Language Server for SystemVerilog.

  • verilog.languageServer.veribleVerilogLs.path (Default: verible-verilog-ls)

    [Experimental] A path to the verible-verilog-ls Language Server binary.

  • verilog.languageServer.rustHdl.enabled (Default: false)

    [Experimental] Enable rust_hdl Language Server for VHDL.

  • verilog.languageServer.rustHdl.path (Default: vhdl_ls)

    [Experimental] A path to the rust_hdl Language Server binary.

  • verilog.formatting.verilogHDL.formatter (Default: verilog-format)

    [Experimental] Choose the Verilog-HDL formatter. Possible values are:

    • verilog-format
    • iStyle
    • verible-verilog-format
  • verilog.formatting.systemVerilog.formatter (Default: verible-verilog-format)

    [Experimental] Choose the Verilog-HDL formatter. Possible values are:

    • verible-verilog-format
  • verilog.formatting.verilogFormat.path (Default: verilog-format)

    [Experimental] A path to the verilog-format binary.

  • verilog.formatting.verilogFormat.settings (Default: ${env:HOME}/.verilog-format.properties)

    [Experimental] A path to the verilog-format settings file.

  • verilog.formatting.iStyleVerilogFormatter.path (Default: iStyle)

    [Experimental] A path to the iStyle Verilog Formatter binary.

  • verilog.formatting.iStyleVerilogFormatter.arguments (Default: nothing)

    [Experimental] Add custom arguments to iStyle Verilog Formatter for formatting.

  • verilog.formatting.iStyleVerilogFormatter.style (Default: Indent only)

    [Experimental] Choose styling options from ANSI/K&R/GNU.

  • verilog.formatting.veribleVerilogFormatter.path (Default: verible-verilog-format)

    [Experimental] A path to the verible-verilog-format binary.

  • verilog.formatting.veribleVerilogFormatter.arguments (Default: nothing)

    [Experimental] Add custom arguments to verible-verilog-format for formatting.

Compatibility

Feature Windows Linux macOS
Basics (like Syntax highlighting) Windows 10 Ubuntu 20.04 macOS 10.15
Icarus Verilog Windows 10 Ubuntu 18.04 Yes
Vivado Logical Simulation Windows 10 Not Tested Not Tested
Modelsim Windows 10 Ubuntu 18.04 Not Tested
Verilator Windows 10 Debian 9 Not Tested
Ctags Integration Windows 10 Ubuntu 18.10 Not Tested
Language Server Windows 10 Ubuntu 20.04 macOS 10.15
Formatting Not tested Ubuntu 20.04 Not tested

If you have tested the linters in new platforms or have issues with them, feel free to file an issue.

Logs

Logs are outputted to LogOutputChannel in th VS Code. You can check it by opening the Output pane in VS Code and choose Verilog in the drop-down menu.

Helpful links

Thanks

vscode-verilog-hdl-support's People

Contributors

andrewnolte avatar ddppt-yy avatar dependabot[bot] avatar eferri avatar hirooih avatar imba-tjd avatar kaz-on avatar kevbroch avatar kikd avatar lasserre avatar limerainne avatar manageryzy avatar mshr-h avatar muratovas avatar nagi1999a avatar nfproc avatar nik-sch avatar noxygen avatar raamakrishnan avatar renovate[bot] avatar retar-kamuy avatar rickluiken avatar sarman1998 avatar sckzw avatar terriblefire avatar thelapinmalin avatar theonekevin avatar tweeklab avatar zeaphoo avatar zoomer-k avatar

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vscode-verilog-hdl-support's Issues

Variables don't work in settings

My project always has a directory with IP cores and I wanted to add the path to this directory to verilator arguments, but they are not processed in any way
"verilog.linting.verilator.arguments." "--error-limit 500 --default-language 1800-2012 --bbox-sys --bbox-unsup -Wall -Wno-DECLFILENAME -Wno-WIDTH -Wno-UNDRIVEN -I${workspaceFolder}/IP
Maybe I'm doing something wrong?

Create snippets only extension

I'm thinking to split this extension into 2 parts.
One for syntax highlighting, the other for simple snippets.

Pros:

  • Easy to maintain
  • You can choose which one you want to use

Cons:

  • It's a little bit messy if you need both extension

Add command to execute linter on current file

The linting occurs only when saving the current file.
However, some verilog files are auto-generated by scripts
or updated by version control applications.

It would be nice to have a command to execute lint on current open file
without the need to edit and save it.

[BUG]cannot peak module definition in another file

Describe the bug
I've got universal-ctags installed, When I ctrl+click a module defined in another file, or reference a module defined in another file, the editor won't take me there / give me a peak of the module's definition.
This is a feature request (sorry if I posted it in the wrong way)

Environment (please complete the following information):

  • OS: Windows 10 1909 build 18363.449
  • VS Code version 1.39.2
  • Extension version 1.0.3
  • iverilog, universal-ctags

Steps to reproduce
Steps to reproduce the behavior:

  1. in work folder, create a file named FOO.sv with module FOO
  2. in work folder, create a file named USE_FOO.sv with module USE_FOO
  3. reference module FOO within USE_FOO
  4. hover your mouse over text "FOO"
  5. right click text FOO, select "go to definition" / "peek definition"

Expected behavior
The editor should appear as if FOO is defined with the same file of module USE_FOO. in step 3/4/5, there shall be a peak of FOO's definition.

Actual behavior
nothing really happens

Additional context
Sorry if this is impossible to implement, I am a student studying the language and the request might be unreasonable. I do think the feature can be helpful (as this is possible in other languages extensions)

Basic operation with ctags

Hello, please forgive me for asking such a basic question. I have your extension installed along with the latest version of universal ctags. I have added the path to the executable in the settings as described in issue #62. I have created a tags file in the folder I want to open. When I open the folder in vscode and open a file in that folder, none of the ctags functionality is present. I assume I am missing a step, but am clueless as to what. Can you help a complete idiot to get this to work?

By the way, I don't have any other ctags support installed, do I need any other extensions? Right now all I have is this one. Would really love to get the ctags to work.

Thanks for your help.

[Support] Xvlog linter does not seem to work

I've just installed the extension and tried to set it up to use xvlog as the linter. I've added "F:\Xilinx\Vivado\2019.1\bin" (which is where my Vivado lives) to my path and from the terminal inside VSC I can run "xvlog" but regardless I don't see any feedback from the linter in my code.

I can't see any relevant output anywhere in the output windows from this extension, so I'm assuming it fails miserably when attempting to run the linter.

Is there any way of getting more logging from it to see what is going on? Any other ideas I can try?

Diagnostic Information from "Run linter" command not removed after closing the file

When the command "Rerun lint tool" is used, the DiagnosticCollection it adds to the document are not being removed.
Steps to reproduce:

  1. Open a file
  2. Run "Rerun linter" command and get some errors
  3. Close the file
  4. The errors are still shown in Explorer and Problems panel, and when opening the file again

The tempLinter in LintManager.ts is being disposed right after the task is done. So, it is not possible to call the removeFileDiagnostics function. Probably need to restructure the class around LintManager and BaseLinter.

Any help here is much appreciated

Inform users on breaking changes

There should be a way to inform the user of breaking changes to the extension. Like when the option of choosing between 2 different linters was added, it broke the extension until I figured out about this change.

A suggestion is to maintain a changelog in the repo. Show a notification when the extension gets updated. And open the changelog file.

Verilator lint support on Windows

I'm trying to run verilator on Win10 using a precompiled binary which has been added to PATH. From the terminal I can run verilator manually and get acceptable output, however when setting the appropriate options to lint using verilator the extension will not report any issues with invalid code. I'm not sure if this is because verilator support is entirely disabled, I notice that the compatibility table indicates that verilator is unavailable (possible owing to its linux-only release), but should the VSCode extension still try to run verilator on Windows when commanded to run a lint check?

iverilog linting

Hi,
I am currently having this error when I execute rerun linting command:

Cannot read property 'removeFileDiagnostics' of null

I have iverilog executable under /usr/bin/, and below are the version info:

Name: Verilog HDL
Id: mshr-h.veriloghdl
Description: Verilog HDL support for VS Code
Version: 0.3.6
Publisher: mshr-h
VS Marketplace Link: https://marketplace.visualstudio.com/items?itemName=mshr-h.veriloghdl

//code
Version: 1.30.0
Commit: c6e592b2b5770e40a98cb9c2715a8ef89aec3d74
Date: 2018-12-11T22:21:33.585Z
Electron: 2.0.12
Chrome: 61.0.3163.100
Node.js: 8.9.3
V8: 6.1.534.41
OS: Linux x64 3.10.0-957.1.3.el7.x86_64

Please tell me what i am missing here. It worked perfectly when I was using windows 10.

Development Plan 2

Our first development plan went great. On to the next!

These are the issues that were either left out unfinished in #25, requested by people or bugs

  1. Auto Alignment (Format Document/Selection) - #25 (comment)
  2. Module hierarchy - #25 (comment)
  3. Choose a different linter for a specific file - #25 (comment)
  4. Preprocessor support - #39
  5. Search for module across workspace and instantiate - #45
  6. Issue with "Rerun linter" - #55
  7. location of work library for modelsim - #59

And these are the new features that I would like to propose:

  1. Defining the workspace
    Currently our tag generation and linting are per file. If we have to move to workspace level tags/linting, the files in the workspace needs to be correctly defined, in the correct order. Most tools use a -f option to pass a file that lists all the files used.

  2. Workspace linting
    With the workspace defined, run the choosen simulator with lint-only or compile-only

  3. Workspace Objects (Ctags for workspace)
    If this is done, a lot of related features of can be implemented (like points 2 & 5 above)

  4. Build Task
    Support running a build task with error parsing from the output (problemMatchers)

  5. Support for Remote-SSH extension
    Have to check if Remote-SSH throws up any new problems

I request you all to propose your ideas/comments.
Thanks.

iverilog linting

Hi,

All my module instantiation in my old code got error: "Unknown module type" after the update.
Simulation and synthesis by vcs and vivado still work.

file-relative includes

First of all: Thanks for your work on this addon, this is by far the nicest solution for Verilog editing I encountered that works well on Linux that isn't just syntax highlighting :)

One quirk of Verilog's include directive is that paths are workdir-relative, not file-relative. This makes organizing things into subfolders rather bothersome and fragile, as changing the directory structure may necessitate changing include directives all over the place.

iverilog supports relative paths with the "-grelative-include"-option:

   -grelative-include|-gno-relative-include
           Enable or disable (default) adding the local files directory to
           the  beginning  of  the  include  file search path. This allows
           files to be included relative to the current file not the  more
           common  files are only found in the working directory or in the
           specified include file search path.

I'd love to use this with your addon. However, adding

"verilog.iverilog.arguments": "-grelative-include"

into the user settings doesn't appear to procure the desired outcome and the default `include behavior is still in effect.

Small example:
verilog-relative-include.zip

In the example, the testbench ("inverter_tb.v") includes the module-under-test via a relative path ("../inverter.v"). The bash script "run_testbench.sh" invokes iverilog with the "-grelative-include" option and executes vvp for simulation. This works fine on the command line - but Visual Studio Code with your addon and the above-mentioned argument cannot find the included file.

Is there something I'm missing?

Can't get CTags to work

Hi,

I am trying to set up CTags to provide outlines, autocompletion, etc. But things will not come together.

I am using Windows 10, latest VSCode, CTags as of today and the most recent Verilog extension. CTags binaries are installed in C:\CTags, propper path is applied in VSCode extension settings.

Any ideas on how to debug?

Best
Sören

Changing the linter in a open project shows output from both the linters

Steps to reproduce

  • Open a project
  • Set the linter to anyone
  • Make some changes, save file and run the linter
  • Change the linter to none
  • Make some changes, save file
  • Set the linter to anyone
  • Make some changes, save file and run the linter again.
  • Output from both the linters are shown

This seems to be a result of a new linter being created, in the configLinter() function, each time the configuration is changed.

I will try to work on it.

Future plans of development

We are at the verge of reaching 50,000 downloads in the marketplace. From this point, I feel it is good to have a structured development plan. The following are a few ideas that I have.

1. Support for more linters

  • Verilator
  • VCS
  • NCsim

2. Merging System Verilog extensions

  • Verilog and System Verilog are very closely related languages. The tools/linters used by Verilog can be used by System Verilog also, at the maximum by turning on a command line switch.
  • Some good features like "Hover over declarations" have been added to mshr-h/vscode-systemverilog-support that this extension can benefit from.
  • "Go To Symbol" like features can be found in eirikpre/VSCode-SystemVerilog

Since there is very little work being done in bringing HDL support to VS code, it is better to pool our resources and knowledge. What do you guys say?

(Update 2018-07-07)

Todo

System Verilog

  • a new branch "sv" in mshr-h/verilog
  • migrate syntax highlighting from mshr-h/sv
  • migrate snippets
  • migrate "Hover variable declaration" (not migrating, creating new)
  • Parse Symbols using Ctags
  • Document Outline
  • Hover variable declaration
  • Definition Provider
  • Intellisense
  • migrate "Module instantiation"
  • migrate "Auto alignment"
  • migrate other features
  • Update iverilog linter to support SV
  • Update xvlog linter to support SV
  • Update modelsim linter to support SV
  • Update Readme, Changelog and other documentation
  • Merge to master and release
  • Deprecate mshr-h/sv

Linters

  • Verilator
  • VCS
  • NCsim

Readme

  • Remove the list of snippets from Readme
  • Table of settings with description and options
  • Mention this issue in the Instructions for Contributors
  • Section for Contributors and prior work

modelsim linting

I don't think it's a particularly good idea to generate a "work" folder in the current directory (although this is a must). Can add an option to specify a location for this "work" folder ?

iverilog.runAtFileLocation does't work

Hi,
First of all thank you for your great work.
I have set
"verilog.linting.iverilog.runAtFileLocation": false
But it seems that this feature does not work.


For example
In a workspace


 [test.v]
module test(
);
endmodule


 [top.v]
module top();
test test1();
endmodule

It will report an error:Unknown module typeiverilog(iverilog)
It will disappear if i add : `include "test.v"
How can I do?
Thank you!

image

Preprocessor support?

I've run into lots of code that uses something like:

https://www.beyond-circuits.com/wordpress/vpp-pl-man-page/

to embed perl into verilog code and generate the eventual .v file. It would be awesome if the user could define 'open' and 'closing' indicators for "this is not verilog" that could be ignored by any of the verilog highlighting that vscode is doing so it doesn't get tripped up. Obviously these sources files won't work with the linter but at least indentation, snippets, etc could still work...hopefully.

if possible could the beginning and end indicators of the perl code be configurable? not all tools use the same "this is not verilog" indicators. :)

[Syntax] Unsized but formatted integer support and integer with under line

The 2 Verlog supported integer was not recognized by this extension.

Unsized formatted integer
'd100
'hff

Underlined integer
100_000

I think following modify of verilog.tmLanguage may solve the 1st one
but not sure if there's any side effect

\b[0-9]+'[bBoOdDhH][a-fA-F0-9_xXzZ]+\b

[0-9]*'[bBoOdDhH][a-fA-F0-9_xXzZ]+\b

Can't seem to match Sublime Text-like syntax highlighting (+ bugs)

sample

Hi,
I'm attempting to use your System Verilog extension for VsCode (+ virtually any Monokai theme) as a replacement for Sublime and its excellent System Verilog plugin and I'm having multiple issues with it:

  1. As you can see with the module instantiation (module_def), the "data" pin gets a blue highlight, but "clk" doesn't.

  2. The module_def and module_instance are completely unhighlighted.

  3. "module" is a completely different color from "endmodule". This doesn't really make sense.

  4. Numbers aren't colored. It would be ideal if they were.

  5. Parameters/Macros/Anything-in-caps should probably be highlighted.

Any way we can make this extension look closer to the Sublime version?

Modelsim linter conflit with SVN extension

When using modelsim linter on a project under SVN (and only with the johnstoncode.svn-scm extension enabled), the linter throw an error on a non existing file.
Strangely, this doesn't impact the two other linters I can use (xvlog and verilator)

If i put syntax error in my file, the new error is shown, but the error on the non existing file is still thrown.

Workaround idea : check file existence before running the linter on the file ?

This is the error returned when copying from the PROBLEMS view :

"resource": "/FILE_DIRECTORY/jtag_common.v.svn",
"owner": "_generated_diagnostic_collection_name_#0",
"code": "modelsim",
"severity": 8,
"message": "** Error: (vlog-7) Failed to open design unit file \"/FILE_DIRECTORY/jtag_common.v.svn\" in read mode.",
"source": "modelsim",
"startLineNumber": 1,
"startColumn": 1,
"endLineNumber": 1,
"endColumn": 1.7976931348623157e+308

Modelsim Linter Not Working

Hi there,

I seem to be having some issues using the modelsim linter. It is installed, and I have put the installation directory (C:\Program Files\IntelFPGA\modelsim_ase\win32aloem) in my PATH variable (and running vlib from cmd does work), but at the top of all *.sv files, I get the following error:

[modelsim] ** Error: (vlog-66) Execution of vlib.exe failed. Please check the error log for more details. [modelsim]

I'm not sure which error log it is talking about, otherwise I would have posted that as well. How do I go about resolving this?

Thank you!

Windows path and spaces

On windows; When opening a .v file in a path that does contain a space, the linter is not working

E.g. C:\my_files\test.v : the linter works
while C:\my files\test.v : the linter is not invoked

various extension support

Can you add an option to just add additional file endings to associate with this extension? I know I've see .v, .vh, .sv, .svh at work. Sometimes others for various reasons.

Verilator lints non-.sv and .v files

vscode-verilog-hdl-support

Verilator should only run on Verilog-HDL with proper Verilog file extensions.

maybe a

verilog.lint.include : [".sv", ".v"] //Verilog HDL/SystemVerilog configuration setting

Invoke linter from specific directory, change default compile target

My projects usually have a dedicated simulation directory where the work library is stored and where there are a few file lists for the RTL and TB. I would like to invoke the command from this directory and supply the file lists, instead of loading whatever the current file is (in a large UVM testbench, linting is useless if I can't compile the entire thing).

Ideally, there should be an override setting where I can completely replace the command arguments, instead of just append arguments to the hard-coded values currently in place.

Here is what the settings look like for SublimeLinter, which you based some of your work off of:

"SublimeLinter.linters.vlog.args": ["-sv -incr -work work -lint -quiet -f files_tb.f"],
"SublimeLinter.linters.vlog.working_dir": "$project_path/verification/uvm/sim",

How to prompt me for syntax errors.

After installing this powerful plugin, my Windows and Linux VsCode don't have the fancy features like the ones you show (with syntax highlighting and auto-completion, but there is no function that can prompt me for syntax errors). I see yours. The sample diagram even has output variables for display. Where am I doing something wrong? Thank you . and i‘m a Chinese Student , English is not good, please forgive me.

there is a color mismatch bug

when i type:
module xadc(
input i_clk_100m,
input i_sig_p,
input i_sig_n,
input i_ref_p,
input i_ref_n,
input i_RESET
);
the last sentence "input i_RESET" display with wrong color.

instantiate module

Systemverilog extension already has instantiation functionality, but it sometimes does not work on verilog files and I only get offered the current file and submodules, but I want to choose from all of my workspace.

Is something like this planned for Verilog as well?

A simple code completion bug

image

When I use tab to complete the keyword "module", Two cursors will appear.
In detail, I write "mod" firstly, then I use tab to complete it. Then it will be
module(
xxx
);
endmodule xxx

xxx represent cursors. The two cursors have the same behavior. If I write codes, they will appear at the two position concurrently.
my vscode run on Windows10

[Non feature request] Create issue template

I was felt that this repository issues is not familiar for developer.
So that, I propose create issue template to like .github/ISSUE_TEMPLATE/issue-template.md for user create good issue easier.

I think bug report requires some information as below.

  • Bug description

  • Environment
    Using OS, VS Code version, color themes, lint tools, etc.
    I think color theme is important information for reproduce syntax highlight issue .

  • Reproduce step (or data)
    Screenshot is easy to know what happens.
    But, that is cannot "copy and paste" to editor, it makes harder reproduce.

  • Expected behavior

  • Actual behavior

  • Additional
    For example, attach screenshot here.


Maybe, some reporter will need feature request template.

[BUG] Cannot read property 'isEmpty' of undefined when attempting to "Go To Definition"

Describe the bug
Unable to use Go To Definition on regular Verilog file

Environment (please complete the following information):

  • OS: Version: Windows 10.0.18362 Build 18362 + SSH Remote to CentOS 6
  • VS Code version: 1.39.2
  • Extension version: 1.0.3
  • color themes, lint tools, etc.

Steps to reproduce
Steps to reproduce the behavior:

  1. Hover over net, port, etc
  2. Press F12 to "Go To Definition"
  3. Watch VS Code do an infinite spin in the top bar.
  4. Look at Log (Window)

Expected behavior
Goes to symbol or says not found.

Actual behavior
Spins indefinitely and nothing happens.

Additional context
Output from Log (Window)

[2019-10-25 15:43:23.775] [renderer1] [error] Cannot read property 'isEmpty' of undefined: TypeError: Cannot read property 'isEmpty' of undefined
	at VerilogHoverProvider.provideHover (/home/tk891973/.vscode-server/extensions/mshr-h.veriloghdl-1.0.3/out/src/providers/HoverProvider.js:13:23)
	at o.asPromise (/home/tk891973/.vscode-server/bin/6ab598523be7a800d7f3eb4d92d7ab9a66069390/out/vs/server/remoteExtensionHostProcess.js:570:169)
	at Promise (/home/tk891973/.vscode-server/bin/6ab598523be7a800d7f3eb4d92d7ab9a66069390/out/vs/server/remoteExtensionHostProcess.js:55:649)
	at new Promise (<anonymous>)
	at Object.t.asPromise (/home/tk891973/.vscode-server/bin/6ab598523be7a800d7f3eb4d92d7ab9a66069390/out/vs/server/remoteExtensionHostProcess.js:55:621)
	at x.provideHover (/home/tk891973/.vscode-server/bin/6ab598523be7a800d7f3eb4d92d7ab9a66069390/out/vs/server/remoteExtensionHostProcess.js:570:140)
	at _withAdapter.e (/home/tk891973/.vscode-server/bin/6ab598523be7a800d7f3eb4d92d7ab9a66069390/out/vs/server/remoteExtensionHostProcess.js:586:653)
	at H._withAdapter (/home/tk891973/.vscode-server/bin/6ab598523be7a800d7f3eb4d92d7ab9a66069390/out/vs/server/remoteExtensionHostProcess.js:583:593)
	at H.$provideHover (/home/tk891973/.vscode-server/bin/6ab598523be7a800d7f3eb4d92d7ab9a66069390/out/vs/server/remoteExtensionHostProcess.js:586:631)
	at p._doInvokeHandler (/home/tk891973/.vscode-server/bin/6ab598523be7a800d7f3eb4d92d7ab9a66069390/out/vs/server/remoteExtensionHostProcess.js:652:275)
	at p._invokeHandler (/home/tk891973/.vscode-server/bin/6ab598523be7a800d7f3eb4d92d7ab9a66069390/out/vs/server/remoteExtensionHostProcess.js:651:971)
	at p._receiveRequest (/home/tk891973/.vscode-server/bin/6ab598523be7a800d7f3eb4d92d7ab9a66069390/out/vs/server/remoteExtensionHostProcess.js:650:588)
	at p._receiveOneMessage (/home/tk891973/.vscode-server/bin/6ab598523be7a800d7f3eb4d92d7ab9a66069390/out/vs/server/remoteExtensionHostProcess.js:649:468)
	at _protocol.onMessage.e (/home/tk891973/.vscode-server/bin/6ab598523be7a800d7f3eb4d92d7ab9a66069390/out/vs/server/remoteExtensionHostProcess.js:647:691)
	at l.fire (/home/tk891973/.vscode-server/bin/6ab598523be7a800d7f3eb4d92d7ab9a66069390/out/vs/server/remoteExtensionHostProcess.js:50:519)
	at _.fire (/home/tk891973/.vscode-server/bin/6ab598523be7a800d7f3eb4d92d7ab9a66069390/out/vs/server/remoteExtensionHostProcess.js:181:274)
	at e.onMessage.e (/home/tk891973/.vscode-server/bin/6ab598523be7a800d7f3eb4d92d7ab9a66069390/out/vs/server/remoteExtensionHostProcess.js:804:104)
	at l.fire (/home/tk891973/.vscode-server/bin/6ab598523be7a800d7f3eb4d92d7ab9a66069390/out/vs/server/remoteExtensionHostProcess.js:50:519)
	at _.fire (/home/tk891973/.vscode-server/bin/6ab598523be7a800d7f3eb4d92d7ab9a66069390/out/vs/server/remoteExtensionHostProcess.js:181:274)
	at t.PersistentProtocol._receiveMessage (/home/tk891973/.vscode-server/bin/6ab598523be7a800d7f3eb4d92d7ab9a66069390/out/vs/server/remoteExtensionHostProcess.js:185:629)
	at _socketDisposables.push._socketReader.onMessage.e (/home/tk891973/.vscode-server/bin/6ab598523be7a800d7f3eb4d92d7ab9a66069390/out/vs/server/remoteExtensionHostProcess.js:182:824)
	at l.fire (/home/tk891973/.vscode-server/bin/6ab598523be7a800d7f3eb4d92d7ab9a66069390/out/vs/server/remoteExtensionHostProcess.js:50:519)
	at p.acceptChunk (/home/tk891973/.vscode-server/bin/6ab598523be7a800d7f3eb4d92d7ab9a66069390/out/vs/server/remoteExtensionHostProcess.js:178:588)
	at _register._socket.onData.e (/home/tk891973/.vscode-server/bin/6ab598523be7a800d7f3eb4d92d7ab9a66069390/out/vs/server/remoteExtensionHostProcess.js:177:958)
	at Socket.t (/home/tk891973/.vscode-server/bin/6ab598523be7a800d7f3eb4d92d7ab9a66069390/out/vs/server/remoteExtensionHostProcess.js:187:68)
	at Socket.emit (events.js:182:13)
	at addChunk (_stream_readable.js:283:12)
	at readableAddChunk (_stream_readable.js:264:11)
	at Socket.Readable.push (_stream_readable.js:219:10)
	at TCP.onStreamRead [as onread] (internal/stream_base_commons.js:94:17)

Fixed number of spaces in snippets

Hello! First of all I'd like to thank you for efforts in development of this extension.

There are 2 fixed spaces in snippets (e.g. "module"). This is a bit annoying to edit the amount of spaces everytime (e.g. I prefer 4). Maybe it's worth to change it to tab (which will be replaced by selected amount of spaces automatically)? 🤔

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