Lack Syntax highlighting for `ifndef about vscode-verilog-hdl-support HOT 3 CLOSED

Could you upload an entire code which reproduces the problem and the screenshot?

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The following in a .v file will show the bug. `ifndef remains gray.

`ifndef __VGA_TIMES_SET_H
    `ifdef vga_480p
        `define __VGA_TIMES_SET_H
		`define ISE_DCM_MULTIPLY		9
		`define ISE_DCM_DIVIDE			15
    `endif // 480p

	`ifndef __VGA_TIMES_SET_H
        `define __VGA_TIMES_SET_H
		// Default 1080p @ 59Hz
		`define ISE_DCM_MULTIPLY		25
		`define ISE_DCM_DIVIDE			7
    `endif
`endif

from vscode-verilog-hdl-support.

@lrenaud Fixed `ifndef syntax highlighting bug on version 1.0.6.
Please check it out.

from vscode-verilog-hdl-support.