Comments (2)
mshr-h
commented on June 1, 2024
Seems to be working in my env.
Code to reproduce
module module_name(
input input_1;
output output_1;
);
case (case_expression)
case_item_1: begin
case_statement_1a;
case_statement_1b;
end
case_item_2 : case_statement_2;
default : case_statement_default;
endcase
casez (case_expression)
case_item_1: begin
case_statement_1a;
case_statement_1b;
end
case_item_2 : case_statement_2;
default : case_statement_default;
endcase
casex (case_expression)
case_item_1: begin
case_statement_1a;
case_statement_1b;
end
case_item_2 : case_statement_2;
default : case_statement_default;
endcase
endmodulefrom vscode-verilog-hdl-support.
danielkasza
commented on June 1, 2024
I tried this again before updating. It was failing when I set the language to Verilog, but it worked in SystemVerilog mode.
The issue is now fixed.
from vscode-verilog-hdl-support.
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from vscode-verilog-hdl-support.