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This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) implemented in 45nm CMOS technology.
侯捷C++课程PPT及代码,动手学起来
:books: 技术面试必备基础知识、Leetcode、计算机操作系统、计算机网络、系统设计、Java、Python、C++
CTR prediction models based on deep learning(基于深度学习的广告推荐CTR预估模型)
Easy-to-use,Modular and Extendible package of deep-learning based CTR models.
【PyTorch】Easy-to-use,Modular and Extendible package of deep-learning based CTR models.
Successive Approximation Register (SAR) ADC Digital Calibration (in Matlab)
This is our implementation of EHCF: Efficient Heterogeneous Collaborative Filtering (AAAI 2020)
高等数学、线性代数、概率论与数理统计、离散数学、大学物理、数字电路与逻辑设计
公众号: 机器学习荐货情报局 所有代码
This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs to construct the 10-bit ADC based on 1-bit per stage pipelined architecture. Models are built in Cadence using ideal components & VerilogA blocks, & Analysis is done on Matlab.
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Verilog HDL/SystemVerilog/Bluespec SystemVerilog support for VS Code
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Machine learning is a way of modeling and interpreting data that allows a piece of software to respond intelligently.
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