It looks like the parser can't handle the final line of the module not having a newline. I'm getting parse errors such as:

Syntax error
ERROR:VerilogModule::_ast: :125: before: / while parsing /some/path/to/verilog.v
endmodule   //modulename<nonewline>

Hi,

Would you mind creating a new release (on PyPI) that uses the latest ply? I saw the latest develop branch is already using ply as a dependency since c057135, which includes dabeaz/ply@cbea715 that fixes import problems in our use cases.

Thank you!

cc @Licheng-Guo

I could not find an API that takes in python code strings options instead of literal files.

It would be really helpful while integrating Pyverilog into other python code.

Currently, just regarray is supported

Hi,

Thanks for the practical tool to parse Verilog. I am wondering whether Pyverilog supports returning start and end position of each node.
If not, any API I can use to extract such information?

Thanks.

Verilog lines such as

parameter    real GTHE3_CHANNEL_RX_PROGDIV_CFG = 0.0,

cause a parse error but should not. Removing "real" works around the problem.

Problem

I found that the current pyverilog.dataflow.signalvisitor and bindvisitor do not support to access a scoped signal (both constant and variable). The corresponding example is testcode/generate.v

Test verilog code

testcode/generate.v

78:         assign subout[j] = subloop[j-1]._subt.tmp ^ subin[j];

The signalvisitor and bindvisitor could not find any corresponding signal ('tmp').

Corresponding functions

signalvisitor.py

• searchScopeConstantDefinition
• searchScopeConstantValue
• functions that use searchConstant***

bindvisitor.py

• searchScopeConstantDefinition
• searchScopeConstantValue
• searchScopeTerminal
• searchScope***
• functions that use searchConstant and searchTerminal

This issue is very heavy.

First off, thanks for creating a nice verilog parser and AST!

I've noticed some issues when parsing escaped identifiers such as:
\wire_name.A[0]

Where I get a parser error because of the ".". Are escaped identifiers supported?

Is there a plan to support SystemVerilog 2012?

Unable to parse task calls using pyverilog.

Failure signature: (fail.log)

Syntax error
Traceback (most recent call last):
  File "task_parse.py", line 5, in <module>
    ast, direct = parse(vfiles, [], [])
  File "/home/vdodeja2/.local/lib/python3.7/site-packages/pyverilog/vparser/parser.py", line 2322, in parse
    ast = codeparser.parse()
  File "/home/vdodeja2/.local/lib/python3.7/site-packages/pyverilog/vparser/parser.py", line 2300, in parse
    ast = self.parser.parse(text, debug=debug)
  File "/home/vdodeja2/.local/lib/python3.7/site-packages/pyverilog/vparser/parser.py", line 77, in parse
    return self.parser.parse(text, lexer=self.lexer, debug=debug)
  File "/home/vdodeja2/.local/lib/python3.7/site-packages/pyverilog/vparser/ply/yacc.py", line 265, in parse
    return self.parseopt_notrack(input,lexer,debug,tracking,tokenfunc)
  File "/home/vdodeja2/.local/lib/python3.7/site-packages/pyverilog/vparser/ply/yacc.py", line 1047, in parseopt_notrack
    tok = self.errorfunc(errtoken)
  File "/home/vdodeja2/.local/lib/python3.7/site-packages/pyverilog/vparser/parser.py", line 2272, in p_error
    self._coord(p.lineno))
  File "/home/vdodeja2/.local/lib/python3.7/site-packages/pyverilog/vparser/plyparser.py", line 55, in _parse_error
    raise ParseError("%s: %s" % (coord, msg))
pyverilog.vparser.plyparser.ParseError: :25: before: (

Verilog code: (task_example.v)

module task_example ();
 
  reg [7:0] r_Mux_Addr_Data = 0;
  reg       r_Addr_Valid = 1'b0;
  reg       r_Data_Valid = 1'b0;
   
  task do_write;
    input [7:0] i_addr, i_data; 
    begin
      // demonstrates driving external Global Reg
      r_Addr_Valid    = 1'b1;
      r_Mux_Addr_Data = i_addr;
      #10;
      r_Addr_Valid    = 1'b0;
      r_Data_Valid    = 1'b1;
      r_Mux_Addr_Data = i_data;
      #10;
      r_Data_Valid = 1'b0;
      #10;
    end
  endtask
      
  always @(*)
    begin
      #10 do_write(8'h01, 8'hBC);
      //do_write(8'h01, 8'hBC);
      //do_write(8'h02, 8'hCD);
    end

   
endmodule

Python script to parse the verilog (task_parse.py)

from pyverilog.vparser.parser import parse

vfiles = ["./task_example.v"]

ast, direct = parse(vfiles, [], [])

ast.show()

Environment:
OS: Ubuntu 18.04.5 LTS
Python version: 3.7
PyVerilog version: 1.2.1

Attaching above files:
task_failure.zip

Hi,

I know the SV support is a work in progress but I thought this syntax was interesting to note.

module module_name import module_name_pkg::*; `MODULE_NAME_PARAM_DECL (

It should be great to have an option to sort the parameter/port/signals/portmap signals in their respective section (module/instance/etc).
I'm trying to compare two differents version of a RTL code (IPs). Between two RTL versions, some signals/ports/parameter name can be not at the same location in the RTL code, or can be remamed. The goal will be to be a visual diff on the parser result of each RTL code to see exactly the modification and find easily the diff.
Without any sorting, it is quite hard to see what is new or different between two RTL code.

Hi,

I'm hitting a parse error that seems to come from YACC but it's no giving a very useful error message. I don't even know what file it is parsing as I'm traversing a hierarchy.

Is there a way to get more info that just the following?

pyverilog.vparser.plyparser.ParseError: :735: before: (

I meet this bug only if I use show as:
ast.show(attrnames = True)
The origin code is:
attrstr = ', '.join('%s=%s' & nv for nv in nvlist)
Probably need to modify the code as:
attrstr = ', '.join(('%s=%s' % (n,v)) for (n,v) in nvlist)

By the way, is there more introductions to your AST and examples?

Hi,

Can I operate pyverilog in windows?
Cause I get the following error, can you assist?

File "C:\Users\bk891828\Box\PyProjects\MyVerilogParser\venv\lib\site-packages\pyverilog\vparser\preprocessor.py", line 64, in preprocess
subprocess.call(cmd)
File "C:\Python\Python38-32\lib\subprocess.py", line 340, in call
with Popen(*popenargs, **kwargs) as p:
File "C:\Python\Python38-32\lib\subprocess.py", line 854, in init
self._execute_child(args, executable, preexec_fn, close_fds,
File "C:\Python\Python38-32\lib\subprocess.py", line 1307, in _execute_child
hp, ht, pid, tid = _winapi.CreateProcess(executable, args,
FileNotFoundError: [WinError 2] The system cannot find the file specified

Thanks,
Boris.

Hi,
I'm trying to generate AST from verilog code but I am facing the error below. I have put the complete address of the verilog file but still it is not locating it. Icarus is already installed in the system.
D:\>Python pyverilog-1.2.1/examples/example_parser.py D:\pyverilog-1.2.1\examples Traceback (most recent call last): File "D:\pyverilog-1.2.1\examples\example_parser.py", line 52, in <module> main() File "D:\pyverilog-1.2.1\examples\example_parser.py", line 43, in main ast, directives = parse(filelist, File "D:\pyverilog-1.2.1\pyverilog\vparser\parser.py", line 2322, in parse ast = codeparser.parse() File "D:\pyverilog-1.2.1\pyverilog\vparser\parser.py", line 2299, in parse text = self.preprocess() File "D:\pyverilog-1.2.1\pyverilog\vparser\parser.py", line 2293, in preprocess self.preprocessor.preprocess() File "D:\pyverilog-1.2.1\pyverilog\vparser\preprocessor.py", line 64, in preprocess subprocess.call(cmd) File "C:\Users\Rimsha's\AppData\Local\Programs\Python\Python39\lib\subprocess.py", line 349, in call with Popen(*popenargs, **kwargs) as p: File "C:\Users\Rimsha's\AppData\Local\Programs\Python\Python39\lib\subprocess.py", line 947, in __init__ self._execute_child(args, executable, preexec_fn, close_fds, File "C:\Users\Rimsha's\AppData\Local\Programs\Python\Python39\lib\subprocess.py", line 1416, in _execute_child hp, ht, pid, tid = _winapi.CreateProcess(executable, args, FileNotFoundError: [WinError 2] The system cannot find the file specified

Hi Anandh,

Thank you! Now I successfully compiled your code by Icarus verilog.
I found that some additional features must be implemented in Pyverilog.
For instance, Pyverilog does not support automatic attribute of function definition.

Give me a little time to modify it ...

Thanks,

Shinya

On 2019/03/06 1:51, anandh krishnan wrote:

Hello Shinya san,

I am very sorry, but please add these two lines in your header file:

parameter P_FLOP_STRUCT_PARITY_ENB = 1'b0;
parameter integer P_FLOP_STRUCT_PARITY_GRAN = 8;

Arrigato.

Thank you,
Anandh

On Monday, March 4, 2019, 8:49:59 PM PST, Shinya TAKAMAEDA-YAMAZAKI <[email protected] mailto:[email protected]> wrote:

Hi Anandh,

Thanks for sharing your codes.

I still have a complication error on Icarus Verilog.
Can you tell me the definitions of P_FLOP_STRUCT_PARITY_GRAN and P_FLOP_STRUCT_PARITY_ENB ?
I could not find the definitions in your main code and header.

$ iverilog -tnull -Wall tmp.v
tmp.v:29: error: Unable to bind parameter P_FLOP_STRUCT_PARITY_GRAN' in ns_s_fifo'
tmp.v:30: error: Unable to bind parameter P_FLOP_STRUCT_PARITY_GRAN' in ns_s_fifo'
tmp.v:32: error: Unable to bind parameter P_FLOP_STRUCT_PARITY_ENB' in ns_s_fifo'
tmp.v:34: error: Unable to bind parameter P_FLOP_STRUCT_PARITY_ENB' in ns_s_fifo'
tmp.v:268: error: Unable to bind parameter P_FLOP_STRUCT_PARITY_ENB' in ns_s_fifo'
tmp.v:268: error: Cannot evaluate genvar conditional expression: P_FLOP_STRUCT_PARITY_ENB
tmp.v:268: error: Unable to bind parameter P_FLOP_STRUCT_PARITY_ENB' in ns_s_fifo'
tmp.v:268: error: Cannot evaluate genvar conditional expression: P_FLOP_STRUCT_PARITY_ENB
8 error(s) during elaboration.

Thanks,

Shinya

On 2019/03/05 13:32, anandh krishnan wrote:

Hello Shinya san,

Please find the header attached.

Thanks,
Anandh

On Monday, March 4, 2019, 7:03:59 PM PST, Shinya TAKAMAEDA-YAMAZAKI <[email protected] mailto:[email protected] <mailto:[email protected] mailto:[email protected]>> wrote:

Hi Anandh,

I'm sorry for the very late response, again.

I tried to read your code by Veriloggen, but I could not do that because I don't have "ns_common_func.vh".
Can you share your header file?

Best regards,

Shinya

On 2019/02/09 5:22, anandh krishnan wrote:

Shinya Sama,

Arrigato Gozaimasu!

I have a fatal error from veriloggen's veriloggen/verilog/from_verilog.py in the routine
visit_GenerateStatement:

"Only generate-for and generate-if statements are supported."

This is because of a "genvar" within my generate block. Please advise what I need to do.
My testcase is:

module ns_s_fifo(
// Outputs
rd_data,
rd_data_valid,
occupancy_cnt,
fifo_full,
perr,
// Inputs
clk,
clk_g,
reset,
wr_enb,
wr_data,
wr_parity,
rd_enb,
perr_inj
);

`include "ns_common_func.vh"

localparam P_FPGA_INFER_RAM        = 1'b0;
parameter P_FIFO_D_WIDTH           = 32;
parameter P_FIFO_DEPTH             = 4;
parameter P_REG_OUT                = 1'b0;
parameter P_OCCUPANCY_CNT          = 1'b0;


parameter P_EXT_PARITY_GEN = 1'b1;
localparam P_DATA_WIDTH_REMAINDER   = P_FIFO_D_WIDTH % P_FLOP_STRUCT_PARITY_GRAN ;
localparam P_DATA_PAD_BITS          = (P_DATA_WIDTH_REMAINDER==0) ? 0 : P_FLOP_STRUCT_PARITY_GRAN - P_DATA_WIDTH_REMAINDER;
localparam P_DATA_PLUS_PAD_WIDTH    = P_FIFO_D_WIDTH + P_DATA_PAD_BITS ;
localparam P_EXT_PARITY_BITS        = ((P_EXT_PARITY_GEN == 1'b0) | (P_FLOP_STRUCT_PARITY_ENB == 1'b0)) ? 1 :
                                       P_DATA_PLUS_PAD_WIDTH / P_FLOP_STRUCT_PARITY_GRAN ;
localparam P_NUM_PARITY_BITS        = P_FLOP_STRUCT_PARITY_ENB ? P_DATA_PLUS_PAD_WIDTH / P_FLOP_STRUCT_PARITY_GRAN : 1 ;



localparam LP_ONE = 1;
localparam P_FIFO_DEPTH_MOD = ((P_FIFO_DEPTH <= 2) & P_REG_OUT) ? 2 :
                              ((P_FIFO_DEPTH >= 3) & P_REG_OUT) ?    (P_FIFO_DEPTH-1) :
                               (P_FIFO_DEPTH <= 1)              ? 2 : P_FIFO_DEPTH ;

localparam P_FIFO_A_WIDTH = (P_FIFO_DEPTH_MOD == 1) ? 1 : clogb2(P_FIFO_DEPTH_MOD) ;
localparam P_OCCU_CNTR_WIDTH = clog2(P_FIFO_DEPTH+1);
localparam [P_FIFO_A_WIDTH-1:0] P_FIFO_DEPTH_MIN_1 = P_FIFO_DEPTH_MOD-1 ;

input                          clk;
input                          clk_g;
input                          reset;

input                          wr_enb;
input [P_FIFO_D_WIDTH-1:0]     wr_data;
input [P_EXT_PARITY_BITS-1:0]  wr_parity;

input                          rd_enb;
output [P_FIFO_D_WIDTH-1:0]    rd_data;
output                         rd_data_valid;

output [P_OCCU_CNTR_WIDTH-1:0] occupancy_cnt;
output                         fifo_full;
// NS_C: Flop Structure Parity I/O
// lint_checking USEPRT off
input                          perr_inj;
// lint_checking USEPRT on
output                         perr;

//**** Signal Declarations ****
reg [P_FIFO_D_WIDTH-1:0] reg_array [P_FIFO_DEPTH_MOD-1:0] /* altera ramstyle = "MLAB, no_rw_check" */ ;
wire [P_FIFO_A_WIDTH-1:0] wr_addrs ;
wire [P_FIFO_A_WIDTH-1:0] rd_addrs ;
wire [P_FIFO_D_WIDTH-1:0] arr_rd_data_d ;
wire [P_FIFO_A_WIDTH:0] wr_pntr_plus1_d ;
wire [P_FIFO_A_WIDTH:0] wr_pntr_bin_d ;
reg [P_FIFO_A_WIDTH:0] wr_pntr_bin_q ;
wire [P_FIFO_A_WIDTH:0] rd_pntr_plus1_d ;
wire [P_FIFO_A_WIDTH:0] rd_pntr_bin_d ;
reg [P_FIFO_A_WIDTH:0] rd_pntr_bin_q ;
wire arr_wen_d ;
wire arr_ren_d ;
wire [P_FIFO_A_WIDTH-1:0] wr_pntr_plusone;
wire [P_FIFO_A_WIDTH-1:0] rd_pntr_plusone;

// synopsys sync_set_reset "reset"

//********************************************************************************
assign wr_pntr_plusone = (wr_pntr_bin_q[P_FIFO_A_WIDTH-1:0] + LP_ONE[P_FIFO_A_WIDTH-1:0]);
assign wr_pntr_plus1_d = (wr_pntr_bin_q[P_FIFO_A_WIDTH-1:0] == P_FIFO_DEPTH_MIN_1) ?
{~(wr_pntr_bin_q[P_FIFO_A_WIDTH]), {(P_FIFO_A_WIDTH){1'b0}}} :
{wr_pntr_bin_q[P_FIFO_A_WIDTH], wr_pntr_plusone[P_FIFO_A_WIDTH-1:0]};
assign wr_pntr_bin_d = arr_wen_d ?
wr_pntr_plus1_d :
wr_pntr_bin_q ;

always @(posedge clk)
begin
if (reset)
wr_pntr_bin_q <= {(P_FIFO_A_WIDTH+1){1'b0}} ;
else
wr_pntr_bin_q <= wr_pntr_bin_d ;
end

assign wr_addrs = wr_pntr_bin_q[P_FIFO_A_WIDTH-1:0] ;

generate
if (P_FPGA_INFER_RAM) begin : G_FPGA
always @(posedge clk)
begin
if (arr_wen_d)
reg_array[wr_addrs] <= wr_data ;
end
end
else begin : G_ASIC
genvar k;
for (k=0; k<P_FIFO_DEPTH_MOD; k=k+1) begin : G_ARR
wire reg_wr_en ;
reg [P_FIFO_D_WIDTH-1:0] reg_q ;

   assign reg_wr_en = arr_wen_d &
                      (wr_addrs == k[P_FIFO_A_WIDTH-1:0]);

   always @(posedge clk_g)
   begin
      if (reg_wr_en)
         reg_q <= wr_data ;
   end

   always @* reg_array[k] = reg_q ;

end

end
endgenerate

assign rd_pntr_plusone = (rd_pntr_bin_q[P_FIFO_A_WIDTH-1:0] + LP_ONE[P_FIFO_A_WIDTH-1:0]);

assign rd_pntr_plus1_d = (rd_pntr_bin_q[P_FIFO_A_WIDTH-1:0] == P_FIFO_DEPTH_MIN_1) ?
{~(rd_pntr_bin_q[P_FIFO_A_WIDTH]), {(P_FIFO_A_WIDTH){1'b0}}} :
{rd_pntr_bin_q[P_FIFO_A_WIDTH], rd_pntr_plusone[P_FIFO_A_WIDTH-1:0]} ;

assign rd_pntr_bin_d = arr_ren_d ?
rd_pntr_plus1_d :
rd_pntr_bin_q ;
always @(posedge clk)
begin
if (reset)
rd_pntr_bin_q <= {(P_FIFO_A_WIDTH+1){1'b0}} ;
else
rd_pntr_bin_q <= rd_pntr_bin_d ;
end

assign rd_addrs = rd_pntr_bin_q[P_FIFO_A_WIDTH-1:0] ;
//lint_checking POOBID OFF
assign arr_rd_data_d = reg_array[rd_addrs] ;
//lint_checking POOBID ON
reg array_empty_q;
reg array_full_q;

always @(posedge clk)
begin
if (reset) begin
array_empty_q <= 1'b1;
array_full_q <= 1'b0;
end
else begin
array_empty_q <= (rd_pntr_bin_d == wr_pntr_bin_d) ;
array_full_q <= (rd_pntr_bin_d[P_FIFO_A_WIDTH] ^ wr_pntr_bin_d[P_FIFO_A_WIDTH]) &
(rd_pntr_bin_d[P_FIFO_A_WIDTH-1:0] == wr_pntr_bin_d[P_FIFO_A_WIDTH-1:0]) ;
end
end

assign fifo_full = array_full_q ;

//********************************************************************************
//Registered output stage
//********************************************************************************
//lint_checking URDWIR OFF
wire pref_stage_wen_d ;
wire pref_from_wr_data;
//lint_checking URDWIR ON
generate
if (P_REG_OUT) begin : G_OREG

   reg                        pref_stage_valid_q ;
   reg [P_FIFO_D_WIDTH -1:0]  pref_stage_data_q ;
   wire [P_FIFO_D_WIDTH -1:0] pref_stage_data_d ;
   assign arr_wen_d = wr_enb & (~array_empty_q | (pref_stage_valid_q & ~rd_enb)) ;
   assign arr_ren_d = rd_enb & ~array_empty_q ;
   assign pref_from_wr_data = (array_empty_q & ~pref_stage_valid_q) |
                              (array_empty_q & pref_stage_valid_q & rd_enb);

   assign pref_stage_data_d = pref_from_wr_data ? wr_data :
                              rd_enb ? arr_rd_data_d :
                              pref_stage_data_q;
   always @(posedge clk) begin
      if (reset)
        pref_stage_data_q <= {(P_FIFO_D_WIDTH){1'b0}} ;
      else
        pref_stage_data_q <= pref_stage_data_d;
   end
   assign pref_stage_wen_d = (wr_enb & array_empty_q & ~pref_stage_valid_q) |
                             (wr_enb & array_empty_q & pref_stage_valid_q & rd_enb) |
                             arr_ren_d ;
   always @(posedge clk)
   begin
      if (reset)
         pref_stage_valid_q <= 1'b0 ;
      else
         if (pref_stage_wen_d)
            pref_stage_valid_q <= 1'b1 ;
         else if (rd_enb)
            pref_stage_valid_q <= 1'b0 ;
   end
   assign rd_data       = pref_stage_data_q ;
   assign rd_data_valid = pref_stage_valid_q ;

end
else begin : G_NO_OREG
   assign arr_wen_d = wr_enb ;
   assign arr_ren_d = rd_enb ;

   assign rd_data       = arr_rd_data_d ;
   assign rd_data_valid = ~array_empty_q ;

   // NS_C : needed for flop structure parity
   assign pref_stage_wen_d = 1'b0;
   assign pref_from_wr_data = 1'b0;
end

endgenerate

generate
if (P_OCCUPANCY_CNT) begin: G_OCCUPANCY_CNT
reg [P_OCCU_CNTR_WIDTH-1:0] occu_cntr;
always @(posedge clk) begin
if (reset) occu_cntr <= {P_OCCU_CNTR_WIDTH{1'b0}};
else if (wr_enb & ~rd_enb) occu_cntr <= occu_cntr + LP_ONE[P_OCCU_CNTR_WIDTH-1:0];
else if (~wr_enb & rd_enb) occu_cntr <= occu_cntr - LP_ONE[P_OCCU_CNTR_WIDTH-1:0];
end
assign occupancy_cnt = occu_cntr;
end
else begin: G_NO_OCCUPANCY_CNT
assign occupancy_cnt = {P_OCCU_CNTR_WIDTH{1'b0}};
end
endgenerate

//********************************************************************************
// Flop Structure Parity
//********************************************************************************
genvar i;
generate
if (P_FLOP_STRUCT_PARITY_ENB) begin : G_FLOP_STRUCT_PARITY

   // lint_checking URAWIR off
   wire [P_DATA_PLUS_PAD_WIDTH-1:0]    padded_wr_data ;
   // lint_checking URAWIR on
   wire [P_DATA_PLUS_PAD_WIDTH-1:0]    padded_rd_data ;
   wire [P_NUM_PARITY_BITS-1:0]        gen_parity;
   wire [P_NUM_PARITY_BITS-1:0]        raw_rd_parity;
   wire [P_NUM_PARITY_BITS-1:0]        rd_parity;
   reg  [P_NUM_PARITY_BITS-1:0]        parity_arr [P_FIFO_DEPTH_MOD-1:0] ;
   wire [P_NUM_PARITY_BITS-1:0]        perr_nxt;
   wire                                force_perr;
   reg                                 perr_q;
   // lint_checking URDREG off
   reg  [P_FIFO_A_WIDTH-1:0]           rd_addrs_q  ;
   // lint_checking URDREG on

   if (P_EXT_PARITY_GEN) begin: G_PARITY_EXT
      assign gen_parity = wr_parity;
   end
   else begin : G_PARITY_GEN
      // NS_C: generate parity
      // NS_C: adjust by pad bits to match the granularity exactly
      assign padded_wr_data = {{P_DATA_PAD_BITS{1'b0}}, wr_data} ;

      for (i=0; i<P_NUM_PARITY_BITS ; i=i+1) begin : G_PARITY_GEN
         assign gen_parity[i] = ^padded_wr_data[P_FLOP_STRUCT_PARITY_GRAN*i+:P_FLOP_STRUCT_PARITY_GRAN];
      end
   end

   always @(posedge clk) begin
      rd_addrs_q <= rd_addrs;
   end


   // NS_C: store parity into array if arr_wen_d = 1
   genvar k;
   for (k=0; k<P_FIFO_DEPTH_MOD; k=k+1) begin : G_PARITY_ARR
      wire parity_wr_en ;
      reg [P_NUM_PARITY_BITS-1:0] parity_q ;

      assign parity_wr_en = arr_wen_d & (wr_addrs == k[P_FIFO_A_WIDTH-1:0]);

      always @(posedge clk_g)
      begin
         if (parity_wr_en)
            parity_q <= gen_parity ;
      end

      always @* parity_arr[k] = parity_q ;
   end


   // NS_C: store/assign pref_stage parity
   if (P_REG_OUT) begin : G_OREG

      reg  [P_NUM_PARITY_BITS-1:0] pref_stage_parity;
      wire [P_NUM_PARITY_BITS-1:0] pref_stage_parity_d;
      // NS_C: Choose the correct parity based on the source of the prefetch load
      assign pref_stage_parity_d = pref_from_wr_data ? gen_parity :
                                   rd_enb ? parity_arr[rd_addrs] :
                                   pref_stage_parity;

      always @(posedge clk) begin
         if (pref_stage_wen_d)
            pref_stage_parity <= pref_stage_parity_d;
      end

      // lint_checking IDXTSM off
      assign raw_rd_parity = pref_stage_parity;
      // lint_checking IDXTSM on

   end // G_OREG

   else begin : G_NO_OREG

      assign raw_rd_parity = parity_arr[rd_addrs];

   end // G_NO_OREG

   // NS_C: force a parity error if programmed to do so
   assign force_perr = perr_inj & rd_enb & (rd_addrs=={P_FIFO_A_WIDTH{1'b0}});
   assign rd_parity = ~force_perr ? raw_rd_parity : ~raw_rd_parity;
   assign padded_rd_data = {{P_DATA_PAD_BITS{1'b0}},rd_data};

   // NS_C: check parity
   for (i=0; i<P_NUM_PARITY_BITS ; i=i+1) begin : G_PARITY_CHECK
         wire data_p_bit;

         assign data_p_bit =  ^padded_rd_data[P_FLOP_STRUCT_PARITY_GRAN*i+:P_FLOP_STRUCT_PARITY_GRAN] ;

         assign perr_nxt[i] = rd_data_valid &  ~(rd_parity[i] == data_p_bit);
   end

   always @(posedge clk) begin
      if (reset) begin
         perr_q <= 1'b0 ;
      end
      else begin
         perr_q <= |perr_nxt ;
      end
   end

   assign perr = perr_q;

end
else begin: G_NO_FLOP_STRUCT_PARITY
   assign perr = 1'b0;
end

endgenerate
//********************************************************************************

`ifdef NS_FIFO_COVERAGE
//lint_checking TPRUSD OFF
// synthesis translate_off

reg done;
always @(posedge clk) begin
   if (~reset) begin
      if (!done && fifo_full===1'b1) begin
         done <= 1'b1;
         $display("%0d: FIFO_FULL_1ST_DETECTED: ns_s_fifo: %m", $time);
      end
   end
end
initial begin
   done <= 1'b0;
   $display("%0d: FIFO_INSTANTIATION: ns_s_fifo: %m", $time);
end

// synthesis translate_on
//lint_checking TPRUSD ON

`endif
endmodule

On Thursday, February 7, 2019, 7:20:56 AM PST, Shinya TAKAMAEDA-YAMAZAKI <[email protected] mailto:[email protected] <mailto:[email protected] mailto:[email protected]> <mailto:[email protected] mailto:[email protected] <mailto:[email protected] mailto:[email protected]>>> wrote:

Hi Anandh,

I'm sorry for the very late response.

"Always" object of Veriloggen has the "self.sensitivity" field. (Please see veriloggen/core/vtypes.py)
A list of Always objects for each Module can be found at "Module.always" field. (Please see veriloggen/core/module.py)

If the Always statement is realized as a sequential circuit, self.sensitivity must be "Posedge" or "Negedge" object.
Otherwise, the field will be None or a list of some signals.

I think the software can predict whether the Always statement is realized as a sequential circuit or not

Thanks again!

Shinya

On 2019/01/25 6:40, anandh krishnan wrote:

Shinya san,

I was able to accomplish this task (computing registers/flip-flop count) in each module
using veriloggen. Thank you Shinya San!. Arrigato.

I also would like to infer always blocks which could be realized as a flip-flop and wished to
get your advice on how to proceed on this. As I need to know the total flipflop count of a module
I need to also add up the costs due to the flipflops which can arise out of the always blocks such
as this-

|module top (q, d, clk) output q; input d, clk; reg q; always @(posedge clk) q = d; endmodule|

On Saturday, January 19, 2019, 6:24:25 PM PST, Shinya TAKAMAEDA-YAMAZAKI <[email protected] mailto:[email protected] <mailto:[email protected] mailto:[email protected]> <mailto:[email protected] mailto:[email protected] <mailto:[email protected] mailto:[email protected]>> <mailto:[email protected] mailto:[email protected] <mailto:[email protected] mailto:[email protected]> <mailto:[email protected] mailto:[email protected] <mailto:[email protected] mailto:[email protected]>>>> wrote:

Hi Anandh,

Thank you for using Pyverilog.

I think you can figure out the number of register by using Veriloggen, not Pyverilog.
Veriloggen is a hardware design framework based on Pyverilog.
Veriloggen can import the existing Verilog HDL design.

Veriloggen: https://github.com/PyHDI/veriloggen

Please see the examples in veriloggen/tests/verilog/from_verilog_/module

Module class has a "variable" member, which contains all "reg"s and "wire"s.

By using isinstance method like "if isinstance(obj, veriloggen.Reg): ...", you can gather only regs from all variables.

Thanks,

Shinya

On 2019/01/20 10:56, anandh krishnan wrote:

Hello Shinya san,

Konnichiwa.

I am trying to leverage PyVerilog AST to count the registers in each
module in my Verilog design. The design is highly parameterized:

An example module from my Verilog design is listed below.

Please help me with pointers on how this can be done with the AST
PyVerilog builds.

Arrigato,
Anandh Krishnan
*
*
*
module ns_noc_data_ppln
#(
parameter P_CLK_SYNCHRONIZER_DEPTH = 2,
parameter P_DATA_WIDTH = 32,
parameter P_DATA_ERRCHK_WIDTH = 4,
parameter P_USRSB_ERRCHK_WIDTH = 4,
parameter P_WC_WIDTH = 2,
parameter P_SB_WIDTH = 15,
parameter P_OUTP_WIDTH = 3,
parameter P_USRSB_WIDTH = 1,
parameter P_NUM_OF_STAGES = 1,
parameter P_VALID_WIDTH = 4,
parameter P_COARSE_CLOCK_GATE = 1,
parameter P_FINE_CLOCK_GATE = 1
) (

 input                            clk,
 input                            reset_n,
 input                            reset_pd_n,
 input                            tst_rst,
 input                            tst_rst_bypass,

 input                            system_cg_or,
 input                            scan_mode,

 input  [P_VALID_WIDTH-1:0]       i_flit_valid,
 input  [P_DATA_WIDTH-1:0]        i_flit_data,
 input  [P_SB_WIDTH-1:0]          i_flit_sb,
 input  [P_USRSB_WIDTH-1:0]       i_flit_usrsb,
 input                            i_flit_type,
 input                            i_flit_mcpkt,
 input                            i_flit_sop,
 input                            i_flit_eop,
 input  [P_WC_WIDTH-1:0]          i_flit_bv,
 input  [P_OUTP_WIDTH-1:0]        i_flit_outp,
 input                            i_pktctl_parity,
 input                            i_rinfo_parity,
 input [P_DATA_ERRCHK_WIDTH-1:0]  i_data_parity,
 input [P_USRSB_ERRCHK_WIDTH-1:0] i_usrsb_parity,

 input                            i_cg_busy,
 output  [P_VALID_WIDTH-1:0]      o_flit_valid,
 output  [P_DATA_WIDTH-1:0]       o_flit_data,
 output  [P_SB_WIDTH-1:0]         o_flit_sb,
 output  [P_USRSB_WIDTH-1:0]      o_flit_usrsb,
 output                           o_flit_type,
 output                           o_flit_mcpkt,
 output                           o_flit_sop,
 output                           o_flit_eop,
 output  [P_WC_WIDTH-1:0]         o_flit_bv,
 output  [P_OUTP_WIDTH-1:0]       o_flit_outp,
 output                           o_pktctl_parity,
 output                           o_rinfo_parity,
 output [P_DATA_ERRCHK_WIDTH-1:0] o_data_parity,
 output [P_USRSB_ERRCHK_WIDTH-1:0]o_usrsb_parity,

 output                           o_cg_busy

) ;

localparam P_DATA_GROUP_WIDTH = P_DATA_WIDTH+P_WC_WIDTH+P_SB_WIDTH+P_USRSB_WIDTH+4+P_OUTP_WIDTH+2+P_DATA_ERRCHK_WIDTH+P_USRSB_ERRCHK_WIDTH ;

wire [P_DATA_GROUP_WIDTH-1:0] in_data_bundle ;
wire [P_DATA_GROUP_WIDTH-1:0] data_ppln [P_NUM_OF_STAGES:0] ;
wire [P_VALID_WIDTH-1:0] valid_ppln [P_NUM_OF_STAGES:0] ;
wire busy_ppln [P_NUM_OF_STAGES:0] ;

assign in_data_bundle = {i_flit_data, i_flit_sb, i_flit_usrsb, i_flit_type, i_flit_mcpkt, i_flit_sop, i_flit_eop, i_flit_bv, i_flit_outp,
i_pktctl_parity, i_rinfo_parity, i_data_parity, i_usrsb_parity} ;

assign data_ppln[0] = in_data_bundle ;
assign valid_ppln[0] = i_flit_valid ;
assign busy_ppln[0] = i_cg_busy ;

generate
genvar i;
for (i=1; i<=P_NUM_OF_STAGES; i=i+1) begin : G_DATA_PPLN
/*
ns_data_ppln_stage AUTO_TEMPLATE (
.i_flit_valid (valid_ppln[i-1]),
.i_flit_data_group (data_ppln[i-1]),
.i_cg_busy (busy_ppln[i-1]),
.o_flit_valid (valid_ppln[i]),
.o_flit_data_group (data_ppln[i]),
.o_cg_busy (busy_ppln[i]),
);
*/
ns_data_ppln_stage #(/AUTOINSTPARAM/
// Parameters
.P_CLK_SYNCHRONIZER_DEPTH(P_CLK_SYNCHRONIZER_DEPTH),
.P_DATA_GROUP_WIDTH (P_DATA_GROUP_WIDTH),
.P_VALID_WIDTH (P_VALID_WIDTH),
.P_COARSE_CLOCK_GATE (P_COARSE_CLOCK_GATE),
.P_FINE_CLOCK_GATE (P_FINE_CLOCK_GATE))
u_ns_data_ppln_stage (/AUTOINST/
// Outputs
.o_flit_valid (valid_ppln[i]), // Templated
.o_flit_data_group (data_ppln[i]), // Templated
.o_cg_busy (busy_ppln[i]), // Templated
// Inputs
.clk (clk),
.reset_n (reset_n),
.tst_rst (tst_rst),
.tst_rst_bypass (tst_rst_bypass),
.reset_pd_n (reset_pd_n),
.system_cg_or (system_cg_or),
.scan_mode (scan_mode),
.i_flit_valid (valid_ppln[i-1]), // Templated
.i_flit_data_group (data_ppln[i-1]), // Templated
.i_cg_busy (busy_ppln[i-1])); // Templated
end
endgenerate

wire [P_DATA_GROUP_WIDTH-1:0] data_ppln_exit;
wire [P_DATA_GROUP_WIDTH-1:0] data_ppln_exit_clean;

assign data_ppln_exit = data_ppln[P_NUM_OF_STAGES];

ifdef NS_ECC_X_SQUASH_DEGREE2 genvar x; generate endgenerate for (x=0; x<P_DATA_GROUP_WIDTH; x=x+1) begin : G_DATA assign data_ppln_exit_clean[x] = (data_ppln_exit[x] === 1'bx) ? in_data_bundle[x]: data_ppln_exit[x]; end else
assign data_ppln_exit_clean = data_ppln_exit;
`endif

assign {o_flit_data, o_flit_sb, o_flit_usrsb, o_flit_type, o_flit_mcpkt, o_flit_sop, o_flit_eop, o_flit_bv, o_flit_outp,
o_pktctl_parity, o_rinfo_parity, o_data_parity, o_usrsb_parity} = data_ppln_exit_clean;
assign o_flit_valid = valid_ppln[P_NUM_OF_STAGES] ;
assign o_cg_busy = busy_ppln[P_NUM_OF_STAGES] ;

endmodule

There is a bug when a constant is assigned in a port map of the module to detect.
The issue is located in the letter that define the type (ie X, H, D, O)
In example:
.VF5_ARI_CAP_NEXTPTR('H000),
.PF0_BAR0_APERTURE_SIZE('B07),
.PF0_BAR0_CONTROL('D7),

I saw that your lexer.py the code to detect a number is lowercase only instead of supporting both uppercase and lowercase.
I think you should change these lines by something like this:
bin_number = '[0-9]'[bB][0-1xz?][0-1xz?]'
octal_number = '[0-9]'[oO][0-7xz?][0-7xz?]'
hex_number = '[0-9]'[hH][0-9a-fA-Fxz?][0-9a-fA-Fxz?]'
decimal_number = '([0-9]'[dD])?[0-9][0-9_]_'

Thanks for your job.

Hello,

I looked in the verilog standard ieee 1364-2005 regarding the partselect adressing. I've created a module base on their example.

module partselect_test
   (input wire [15:0] big_vect,
    input wire [0:15] little_vect,

    output wire [7:0] big_part1,
    output wire [7:0] big_part2,

    output wire [0:7] little_part1,
    output wire [0:7] little_part2);

    assign big_part1 = big_vect[ 0 +: 8]; // == big_vect[ 7 : 0]
    assign big_part2 = big_vect[15 -: 8]; // == big_vect[15 : 8]

    assign little_part1 = little_vect[ 0 +: 8]; // == little_vect[0 :  7]
    assign little_part2 = little_vect[15 -: 8]; // == little_vect[8 : 15]

endmodule

When I parsed the code, I obtained the following AST (I've put only the assign nodes) :

      Assign:  (at 11)
        Lvalue:  (at 11)
          Identifier: big_part1 (at 11)
        Rvalue:  (at 11)
          Partselect:  (at 11)                   // The partselect parsed is [0:8]
            Identifier: big_vect (at 11)         // The standard says [7:0]
            IntConst: 0 (at 11)
            Plus:  (at 11)
              IntConst: 0 (at 11)
              IntConst: 8 (at 11)
      Assign:  (at 12)
        Lvalue:  (at 12)
          Identifier: big_part2 (at 12)
        Rvalue:  (at 12)
          Partselect:  (at 12)                     // The partselect parsed is [15:7]
            Identifier: big_vect (at 12)           // The standard says [15:8]
            IntConst: 15 (at 12)
            Minus:  (at 12)
              IntConst: 15 (at 12)
              IntConst: 8 (at 12)
      Assign:  (at 14)
        Lvalue:  (at 14)
          Identifier: little_part1 (at 14)
        Rvalue:  (at 14)
          Partselect:  (at 14)                     // The partselect parsed is [0:8]
            Identifier: little_vect (at 14)        // The standard says [0:7]
            IntConst: 0 (at 14)
            Plus:  (at 14)
              IntConst: 0 (at 14)
              IntConst: 8 (at 14)
      Assign:  (at 15)
        Lvalue:  (at 15)
          Identifier: little_part2 (at 15)
        Rvalue:  (at 15)
          Partselect:  (at 15)                     // The partselect parsed is [15:7]
            Identifier: little_vect (at 15)        // The standard says [8:15]
            IntConst: 15 (at 15)
            Minus:  (at 15)
              IntConst: 15 (at 15)        
              IntConst: 8 (at 15)

I think that you cannot resolve the "+:" or "-:" without analyzing the declaration of the variable to know if the bit range is ascending or descending (see parser.py lines 726, 731, 741, 746).

In my opinion the best way to manage this issue would be to create a new node type (PartselectDynamic for instance). This node would be instantiated by the parser when the tokens PLUSCOLON or MINUSCOLON are found. The codegen would be easy to modify, but I don't know the impact on the other parts of PyVerilog.

I can try this solution if you want.

Christophe

As title says, using the reorder option causes a namespace conflict on the name reorder in dataflow/graphgen.py:


The fix should be easy, I could do a pull request if you want but I was wondering if you have a naming convention to follow to fix this issue.

In the attached example, the parser can't process the .mem({ \mem[0][0] , \mem[0][1] , \mem[1][0] , \mem[1][1] }) in the module header.

Iverilog compiles the verilog file without flagging any syntax errors, so I assume it is valid verilog.

test.zip

Hi,
how can I replace all the occurrences of a specific verilog parameter with their value?
I mean, suppose I have "parameter [3:0] x = 4'b3;" and then a lot of usages of x, I'd need to effectively remove the parameter and replace every occurrence of x with 4'b3.

Thanks

Source: (at 10)
Description: (at 10)
ModuleDef: fsm (at 10)
Paramlist: (at 0)
Portlist: (at 10)
Port: clk, None (at 10)
Port: a, None (at 10)
Port: out1, None (at 10)
Port: out2, None (at 10)
Decl: (at 11)
Input: clk, False (at 11)
Decl: (at 12)
Input: a, False (at 12)
Decl: (at 13)
Output: out1, False (at 13)
Decl: (at 14)
Output: out2, False (at 14)
Decl: (at 16)
Reg: state, False (at 16)
Width: (at 16)
IntConst: 2 (at 16)
IntConst: 0 (at 16)
Decl: (at 19)
Parameter: IDLE, False (at 20)
Rvalue: (at 20)
IntConst: 3'b001 (at 20)
Width: (at 19)
IntConst: 2 (at 19)
IntConst: 0 (at 19)
Parameter: STATE_1, False (at 20)
Rvalue: (at 21)
IntConst: 3'b010 (at 21)
Width: (at 19)
IntConst: 2 (at 19)
IntConst: 0 (at 19)
Parameter: FINAL, False (at 20)
Rvalue: (at 22)
IntConst: 3'b100 (at 22)
Width: (at 19)
IntConst: 2 (at 19)
IntConst: 0 (at 19)
Assign: (at 25)
Lvalue: (at 25)
Identifier: out1 (at 25)
Rvalue: (at 25)
Eq: (at 25)
Identifier: state (at 25)
Identifier: STATE_1 (at 25)
Assign: (at 26)
Lvalue: (at 26)
Identifier: out2 (at 26)
Rvalue: (at 26)
Eq: (at 26)
Identifier: state (at 26)
Identifier: FINAL (at 26)
Always: (at 29)
SensList: (at 29)
Sens: posedge (at 29)
Identifier: clk (at 29)
Block: None (at 29)
CaseStatement: (at 30)
Identifier: state (at 30)
Case: (at 31)
Identifier: IDLE (at 31)
IfStatement: (at 32)
Identifier: a (at 32)
Block: None (at 32)
NonblockingSubstitution: (at 33)
Lvalue: (at 33)
Identifier: state (at 33)
Rvalue: (at 33)
Identifier: STATE_1 (at 33)
Block: None (at 34)
NonblockingSubstitution: (at 35)
Lvalue: (at 35)
Identifier: state (at 35)
Rvalue: (at 35)
Identifier: IDLE (at 35)
Case: (at 37)
Identifier: STATE_1 (at 37)
IfStatement: (at 38)
Identifier: a (at 38)
Block: None (at 38)
NonblockingSubstitution: (at 39)
Lvalue: (at 39)
Identifier: state (at 39)
Rvalue: (at 39)
Identifier: FINAL (at 39)
Block: None (at 40)
NonblockingSubstitution: (at 41)
Lvalue: (at 41)
Identifier: state (at 41)
Rvalue: (at 41)
Identifier: IDLE (at 41)
Case: (at 43)
Identifier: FINAL (at 43)
IfStatement: (at 44)
Identifier: a (at 44)
Block: None (at 44)
NonblockingSubstitution: (at 45)
Lvalue: (at 45)
Identifier: state (at 45)
Rvalue: (at 45)
Identifier: FINAL (at 45)
Block: None (at 46)
NonblockingSubstitution: (at 47)
Lvalue: (at 47)
Identifier: state (at 47)
Rvalue: (at 47)
Identifier: IDLE (at 47)
Case: (at 49)
NonblockingSubstitution: (at 50)
Lvalue: (at 50)
Identifier: state (at 50)
Rvalue: (at 50)
Identifier: IDLE (at 50)

Test the module which contain the funtion code in it, then I got error.
I check the code of lex. It has the key word "function". So I guess that I have to modify yacc to make it work well.

I already have run the pyverilog well with some simple verilog code which do not have function in it.

Pyverilog doesn't parse include and define statements. I've shown a simple example below, but this applies to circuits with a define.v file with hundreds of defined variables shared among the rest of the .v files in the circuit.

I've attached some files so that the error can be reproduced. To reproduce the error, unzip the circuit 1000base-x (taken from OpenCores.com) and download & rename (from .txt to .py) the no_parse_include.py file. Add f=open("output.txt", "w+") under line 2315 and f.write(text) under the new line 2317 in path_to_pyverilog/vparser.py. Run in terminal: py no_parse_include.py 1000base-x\. Notice you get the error pyverilog.vparser.parser.ParseError: None: at end of input. If you open the output.txt file, the parser failed on the line include "timescale.v" in the file clean_rst.v. If this line is commented out, pyverilog supposedly completes but the output parsed stops before the same line in decoder_8b10b.v (I've included my .txt version).

Commenting out the include statement in all files will allow pyverilog to complete with the correct output with the caveat that all defined variables in the include file will have to be copied over locally to all files. Include statements in verilog files are really common and copying variable is very tedious, so I wondered if it might be possible to include a fix for pyverilog parsing function.

Additionally, I've been looking for extra opensource circuits that are successfully parsed by pyverilog to test my application with. I would really appreciate any help in this area!

Thanks,
Kristyn
output.txt
1000base-x_latest (1).tar.gz
no_parse_include.txt

Hi,

My p_sram.v and my python file are as attached files and the version of verilog code parser is 1.1.1.
attached.zip
After parsing the p_sram.v, it shows out the below error. I think it parser does not support the two-dimensional array like reg [7:0] test_r [127:0][63:0]. Would you please reproduce my case?
Thank you
-----------error------------------------------------
Generating LALR tables
WARNING: 160 shift/reduce conflicts
Syntax error
Traceback (most recent call last):
File "./gen_sram.py", line 164, in
main()
File "./gen_sram.py", line 116, in main
preprocess_define=options.define)
File "/CAD/Anaconda2/4.4.0/lib/python2.7/site-packages/pyverilog/vparser/parser.py", line 2225, in parse
ast = codeparser.parse()
File "/CAD/Anaconda2/4.4.0/lib/python2.7/site-packages/pyverilog/vparser/parser.py", line 2211, in parse
ast = self.parser.parse(text, debug=debug)
File "/CAD/Anaconda2/4.4.0/lib/python2.7/site-packages/pyverilog/vparser/parser.py", line 64, in parse
return self.parser.parse(text, lexer=self.lexer, debug=debug)
File "/CAD/Anaconda2/4.4.0/lib/python2.7/site-packages/pyverilog/vparser/ply/yacc.py", line 265, in parse
return self.parseopt_notrack(input,lexer,debug,tracking,tokenfunc)
File "/CAD/Anaconda2/4.4.0/lib/python2.7/site-packages/pyverilog/vparser/ply/yacc.py", line 1047, in parseopt_notrack
tok = self.errorfunc(errtoken)
File "/CAD/Anaconda2/4.4.0/lib/python2.7/site-packages/pyverilog/vparser/parser.py", line 2184, in p_error
self._coord(p.lineno))
File "/CAD/Anaconda2/4.4.0/lib/python2.7/site-packages/pyverilog/vparser/plyparser.py", line 54, in _parse_error
raise ParseError("%s: %s" % (coord, msg))
pyverilog.vparser.plyparser.ParseError: :22: before: [

I've just hit a parse error that seems strange. In parser.py, why does p_taskvardecl not include a check for the Output type?

def p_taskvardecl(self, p):
        """taskvardecl : decl
        | integerdecl
        """
        if isinstance(p[1], Decl):
            for r in p[1].list:
                if (not isinstance(r, Input) and not isinstance(r, Reg) and
                        not isinstance(r, Integer)):
raise ParseError("Syntax Error")

Hi ,

X-mas Greetings.
I am a newbie, how can I extract the features from by Verilog file to prepare a dataset for applying deep learning? Any colab or notebook help?

Thanks,
Suti

Can someone give a short introduction about how to code case statements using ast? Thanks!

I want to output a AST file ,after command' python3 pyverilog/examples/example_parser.py test.v' . i get' Generating LALR tables'

Source: (at 1)
Description: (at 1)
ModuleDef: TOP (at 1)
Paramlist: (at 0)
Portlist: (at 1)
Port: CLK, None (at 1)
Port: RST, None (at 1)
Decl: (at 2)
Input: CLK, False (at 2)
Input: RST, False (at 2)
Decl: (at 3)
Reg: cnt, False (at 3)
Width: (at 3)
IntConst: 7 (at 3)
IntConst: 0 (at 3)
Always: (at 4)
SensList: (at 4)
Sens: posedge (at 4)
Identifier: CLK (at 4)
Block: None (at 4)
IfStatement: (at 5)
Identifier: RST (at 5)
Block: None (at 5)
NonblockingSubstitution: (at 6)
Lvalue: (at 6)
Identifier: cnt (at 6)
Rvalue: (at 6)
IntConst: 0 (at 6)
Block: None (at 7)
CaseStatement: (at 8)
Identifier: cnt (at 8)
Case: (at 9)
IntConst: 'h0 (at 9)
IntConst: 'h1 (at 9)
IntConst: 'h2 (at 9)
Block: None (at 9)
NonblockingSubstitution: (at 10)
Lvalue: (at 10)
Identifier: cnt (at 10)
Rvalue: (at 10)
Plus: (at 10)
Identifier: cnt (at 10)
IntConst: 1 (at 10)
Case: (at 12)
IntConst: 'hff (at 12)
Block: None (at 12)
NonblockingSubstitution: (at 13)
Lvalue: (at 13)
Identifier: cnt (at 13)
Rvalue: (at 13)
IntConst: 0 (at 13)
Case: (at 15)
Block: None (at 15)
NonblockingSubstitution: (at 16)
Lvalue: (at 16)
Identifier: cnt (at 16)
Rvalue: (at 16)
Plus: (at 16)
Identifier: cnt (at 16)
IntConst: 1 (at 16)
this is AST? if not ,what i should do to get ast?

Currently, pyverilog recognize clock and reset signal by their name at bind_visitor._createAlwaysinfo.

But I hope to be implemented other method using if branch structure (as command-line option or default).

That is, if the first "if" branch conditions is a signal in the sensitivity list, it should be determined as reset.

i.e.

def _is_reset(self, node, sig):
    if not isinstance(node.statement.statements[0], pyverilog.vparser.ast.IfStatement):
        return False
    if isinstance(node.statement.statements[0].cond, pyverilog.vparser.ast.Ulnot) and edge == 'negedge':
        target = node.statement.statements[0].cond.children()[0]
    elif edge == 'posedge':
        target = node.statement.statements[0].cond
    else:
        return False

    if isinstance(target, pyverilog.vparser.ast.Pointer):
        if sig.ptr == target.ptr:
            target = target.var
        else:
            return False

    return target == sig

I look forward to listening your opinion when there is your time.

The current parser may not be able to parse the code as below.

function integer funcname;
  input invalue;
  // ...
  funcname = 0;
endfunction

Can I write test integration script for the environment which can't use 'make' command?

I want to write it by simple Python or travis CI (If you want).

The filelist include defines related files, IP modules files, but after I start to read the filelist within example_parser.py, it generate below errors:
Syntax error
Traceback (most recent call last):
File "/pkg/eclipse-/4.2.1-dvt3.2.2/x86_64-linux/plugins/org.python.pydev_2.7.1.2012100913/pysrc/pydevd.py", line 1397, in
debugger.run(setup['file'], None, None)
File "/pkg/eclipse-/4.2.1-dvt3.2.2/x86_64-linux/plugins/org.python.pydev_2.7.1.2012100913/pysrc/pydevd.py", line 1090, in run
pydev_imports.execfile(file, globals, locals) #execute the script
File "/pkg/eclipse-/4.2.1-dvt3.2.2/x86_64-linux/plugins/org.python.pydev_2.7.1.2012100913/pysrc/_pydev_execfile.py", line 38, in execfile
exec(compile(contents+"\n", file, 'exec'), glob, loc) #execute the script
File "/home/iverilog/python37/lib/python3.7/site-packages/pyverilog/joe/jojo/example_parser.py", line 61, in
main()
File "/home/iverilog/python37/lib/python3.7/site-packages/pyverilog/joe/jojo/example_parser.py", line 45, in main
preprocess_define=options.define)
File "/home/iverilog/python37/lib/python3.7/site-packages/pyverilog/vparser/parser.py", line 2322, in parse
ast = codeparser.parse()
File "/home/iverilog/python37/lib/python3.7/site-packages/pyverilog/vparser/parser.py", line 2300, in parse
ast = self.parser.parse(text, debug=debug)
File "/home/iverilog/python37/lib/python3.7/site-packages/pyverilog/vparser/parser.py", line 77, in parse
return self.parser.parse(text, lexer=self.lexer, debug=debug)
File "/home/iverilog/python37/lib/python3.7/site-packages/pyverilog/vparser/ply/yacc.py", line 265, in parse
return self.parseopt_notrack(input,lexer,debug,tracking,tokenfunc)
File "/home/iverilog/python37/lib/python3.7/site-packages/pyverilog/vparser/ply/yacc.py", line 1047, in parseopt_notrack
tok = self.errorfunc(errtoken)
File "/home/iverilog/python37/lib/python3.7/site-packages/pyverilog/vparser/parser.py", line 2272, in p_error
self._coord(p.lineno))
File "/home/iverilog/python37/lib/python3.7/site-packages/pyverilog/vparser/plyparser.py", line 55, in _parse_error
raise ParseError("%s: %s" % (coord, msg))
pyverilog.vparser.plyparser.ParseError: :1: before: /

Hi, I followed installation instructions on MacOS 10.14.6 and all is good. Then I get this error with the example_parser on test.v

Traceback (most recent call last):
File "examples/example_parser.py", line 10, in
import pyverilog.utils.version
ModuleNotFoundError: No module named 'pyverilog.utils.version'

In some hardware designs, initial statements are utilized to set initial values of registers and memory cells. However the current dataflow analyzer in Pyverilog does not support the initial statement completely.

after i got syntax analysis from pyverilog. The code generator is more like " writing verilog code by using python" for me.

I am trying to initiate the module inside my file. But i am not aware of the syntax that how to use InstanceList and Instance function to initiate a module.

See #77

Hi, I try to parse cell library, and getting error near delay statement. Here is example:

test.v:

module MODULE_NAME(Q);
    not #(1) (Q);
endmodule

main.py:

from pyverilog.vparser.parser import parse
lib_ast, lib_directives = parse(["test.v"])

And I got this Traceback:

λ python main.py
Syntax error
Traceback (most recent call last):
  File "main.py", line 7, in <module>
    lib_ast, lib_directives = parse(["test.v"])
  File "C:\Miniconda2\lib\site-packages\pyverilog\vparser\parser.py", line 2110, in parse
    ast = codeparser.parse()
  File "C:\Miniconda2\lib\site-packages\pyverilog\vparser\parser.py", line 2098, in parse
    ast = self.parser.parse(text, debug=debug)
  File "C:\Miniconda2\lib\site-packages\pyverilog\vparser\parser.py", line 63, in parse
    return self.parser.parse(text, lexer=self.lexer, debug=debug)
  File "C:\Miniconda2\lib\site-packages\pyverilog\vparser\ply\yacc.py", line 265, in parse
    return self.parseopt_notrack(input,lexer,debug,tracking,tokenfunc)
  File "C:\Miniconda2\lib\site-packages\pyverilog\vparser\ply\yacc.py", line 1047, in parseopt_notrack
    tok = self.errorfunc(errtoken)
  File "C:\Miniconda2\lib\site-packages\pyverilog\vparser\parser.py", line 2074, in p_error
    self._coord(p.lineno))
  File "C:\Miniconda2\lib\site-packages\pyverilog\vparser\plyparser.py", line 54, in _parse_error
    raise ParseError("%s: %s" % (coord, msg))
pyverilog.vparser.plyparser.ParseError: :2: before: (

I am trying to expand the lexer to add more tokens. However I am running into a issue I can't figure out.

Here is my test error:

python /pyverilog-1.1.3/examples/example_parser.py -D CLK test.v
WARNING: Token 'ALWAYS_FF' defined, but not used
WARNING: Token 'ALWAYS_COMB' defined, but not used
WARNING: Token 'LOGIC' defined, but not used
WARNING: There are 3 unused tokens
Generating LALR tables
WARNING: 160 shift/reduce conflicts
Syntax error
Traceback (most recent call last):
File "/nfs/sc/disks/sdg74_2970/pyverilog-1.1.3/examples/example_parser.py", line 52, in
main()
File "/nfs/sc/disks/sdg74_2970/pyverilog-1.1.3/examples/example_parser.py", line 45, in main
preprocess_define=options.define)
File "/nfs/sc/disks/sdg74_2970/pyverilog-1.1.3/pyverilog/vparser/parser.py", line 2225, in parse
ast = codeparser.parse()
File "/nfs/sc/disks/sdg74_2970/pyverilog-1.1.3/pyverilog/vparser/parser.py", line 2211, in parse
ast = self.parser.parse(text, debug=debug)
File "/nfs/sc/disks/sdg74_2970/pyverilog-1.1.3/pyverilog/vparser/parser.py", line 64, in parse
return self.parser.parse(text, lexer=self.lexer, debug=debug)
File "/nfs/sc/disks/sdg74_2970/pyverilog-1.1.3/pyverilog/vparser/ply/yacc.py", line 265, in parse
return self.parseopt_notrack(input,lexer,debug,tracking,tokenfunc)
File "/nfs/sc/disks/sdg74_2970/pyverilog-1.1.3/pyverilog/vparser/ply/yacc.py", line 1047, in parseopt_notrack
tok = self.errorfunc(errtoken)
File "/nfs/sc/disks/sdg74_2970/pyverilog-1.1.3/pyverilog/vparser/parser.py", line 2184, in p_error
self._coord(p.lineno))
File "/nfs/sc/disks/sdg74_2970/pyverilog-1.1.3/pyverilog/vparser/plyparser.py", line 54, in _parse_error
raise ParseError("%s: %s" % (coord, msg))
pyverilog.vparser.plyparser.ParseError: :10: before: logic

Here is my test.v:
ifndef TOP define TOP

module top
(
ifndef CLK input vcc, endif
input wire CLK,
input logic RST,
input enable,
input [31:0] value,
output logic [7:0] led
);
reg [31:0] count;
reg [7:0] state;
assign led = count[23:16];
always_ff @(posedge CLK) begin
if(RST) begin
count <= 0;
state <= 0;
end else begin
if(state == 0) begin
if(enable) state <= 1;
end else if(state == 1) begin
state <= 2;
end else if(state == 2) begin
count <= count + value;
state <= 0;
end
end
end
endmodule
`endif

I added these keywords:

keywords = (
'MODULE', 'ENDMODULE', 'BEGIN', 'END', 'GENERATE', 'ENDGENERATE', 'GENVAR',
'FUNCTION', 'ENDFUNCTION', 'TASK', 'ENDTASK',
'INPUT', 'INOUT', 'OUTPUT', 'TRI', 'REG', 'WIRE', 'INTEGER', 'REAL', 'SIGNED',
'PARAMETER', 'LOCALPARAM', 'SUPPLY0', 'SUPPLY1',
'ASSIGN', 'ALWAYS', 'ALWAYS_FF', 'ALWAYS_COMB', 'SENS_OR', 'POSEDGE', 'NEGEDGE', 'INITIAL',
'IF', 'ELSE', 'FOR', 'WHILE', 'CASE', 'CASEX', 'ENDCASE', 'DEFAULT',
'WAIT', 'FOREVER', 'DISABLE', 'FORK', 'JOIN', 'LOGIC',
)

If you have any guidance, it would be appreciated.

While using parser all defparam statments returns error like this:
pyverilog.vparser.plyparser.ParseError: :145: before: .

In dataflow/bindvisitor.py I am seeing an issue in getDsts where left is an Concat object instead of an LConcat object which looking at the code I posted below is just a matter of naming scheme. If you add the following change it will fix this issue and treat them as the same. This is happening when using a dataflow analyzer feel free to contact me to reproduce the error.

• 1277 if isinstance(left, LConcat):

• 1277 if isinstance(left, Concat) or isinstance(left, LConcat):

266 class Concat(Node):
267 attr_names = ()
268 def init(self, list, lineno=0):
269 self.lineno = lineno
270 self.list = list
271 def children(self):
272 nodelist = []
273 if self.list: nodelist.extend(self.list)
274 return tuple(nodelist)
275 class LConcat(Concat): pass

The following syntax doesn't compile in Pyverilog

assign (weak1,weak0) vreg1p65= 1'b1;

It seems like instance names are currently required by the parser. However, they are not always needed in the case of gate primitives like: and, or, not, etc. Example:

and(out1, in1, in2);

Thanks for your excellent work, but I found it unsupport some operation when parse dataflow graph. The error message it returns is :

File "/usr/local/lib/python3.5/dist-packages/pyverilog-1.1.3.dev0-py3.5.egg/pyverilog/dataflow/bindvisitor.py", line 1339, in getDst
    (str(type(left)), str(left)))
pyverilog.utils.verror.FormatError: unsupported AST node type: <class 'pyverilog.vparser.ast.Concat'> <pyverilog.vparser.ast.Concat object at 0x7fa687524f98>

it seems that the function getDst in dataflow/bindvisitor.py does not support vparser.ast.concat operation.
My verilog source code in attach files. And the top module I want parse is one_round module.
verilogsrc.zip
Hope the tool could be better and I can also do something for the project if possible.

please tell how to convert verilog to ast code by pyverilog