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Hello world šŸ‘‹

  • šŸ”­ Iā€™m currently working (hard!) on my PhD in Computer Engineering @ Politecnico di Torino on "System-Level-Test techniques for Automotive SoCs"
  • M.Sc. in Embedded Systems Engineering @ Politecnico di Torino, Italy, A.Y. 2020.
  • Erasmus Student @ Chalmers University of Technology during A.Y. 2019/2020
  • šŸŒ± Iā€™m currently learning.
  • šŸ‘Æ Iā€™m looking to collaborate on Real-Time Operating Systems

š— š˜† š—§š—²š—°š—ø š—¦š˜š—®š—°š—ø

Python C++ Shell AssemblyScript

Ansible Git GitLab GitHub

TCL - System Verilog - Verilog - VHDL

š—¦š˜š—®š˜š˜€

franout's github stats

Francesco Angione's Projects

cth_hpc icon cth_hpc

High parallel computing @ Chalmers University of technology

fpu icon fpu

IEEE 754 floating point unit in Verilog

fpuvhdl icon fpuvhdl

Floating Point Adder and Multiplier

freertos-kernel icon freertos-kernel

FreeRTOS kernel files only, submoduled into https://github.com/FreeRTOS/FreeRTOS and various other repos.

hdfit icon hdfit

HDFIT (Hardware Design Fault Injection Toolkit) Github documentation pages.

hdfit.scriptshpc icon hdfit.scriptshpc

This repository contains an HPC (High Performance Computing) reliability benchmark, carrying out fault injection experiments on a variety of HPC applications, targeting BLAS (Basic Linear Algebra Subroutines) GEMM (GEneral Matrix Multiply) operations.

hw icon hw

RTL, Cmodel, and testbench for NVDLA

opendcdiag icon opendcdiag

OpenDCDiag is an open-source project designed to identify defects and bugs in CPUs. It consists of a set of tests built around a sophisticated CPU testing framework.

tensorflow icon tensorflow

An Open Source Machine Learning Framework for Everyone

tensorflow_for_pynqz2 icon tensorflow_for_pynqz2

tensorflor 2.1 wheel for pynq z2 ( zynq 7000 xilinx SoC ), cross compiled with different compiler's flags using the script provided by tensorflow for building it for rasberry

vcddiff icon vcddiff

Basic VCD comparison tool, for Verilator testing

verilator icon verilator

Verilator open-source SystemVerilog simulator and lint system

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