Comments (2)
I've only used this with the ModuleDef node, but a quick scan of the code (https://github.com/PyHDI/Pyverilog/blob/d78ee0f2004cbc0b370d20c20b1bac31f55c41a5/pyverilog/vparser/parser.py and https://github.com/PyHDI/Pyverilog/blob/a1bf312e9608ba47d3724dacbb98928b66ef561c/pyverilog/vparser/ast.py for example) it seems that most nodes provide the lineno
attribute for the line number, the moduledef node also provides an end_lineno
attribute for the end.
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Thanks for your hint :)
I read the code. Yeah, we can get the line number of each node in the AST. However, I still want to extract the exact start and end position of each node like ASTNode provided by JDT, since I want to compare two ASTs of Verilog.
Do you @leonardt think we can use Pyverilog to get this step? Or any other parser?
Thanks.
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Related Issues (20)
- dataflow analysis error HOT 1
- Parsing Error for integer memories
- Parse Error for Inverter Gate
- Parser Error for resettable D Flip-Flop HOT 1
- ParseError for User Defined Primitives HOT 1
- Parsing Issues HOT 1
- Specify statements
- Unsized numbers without base not supported HOT 2
- TypeError: generate() got an unexpected keyword argument 'reorder' HOT 3
- unsufficient parse for large scale verilog design
- Can not support "generate case" statement
- AST node HOT 1
- Preprocessing Issue when included file is in different directory HOT 1
- Parse Error: Cannot parse a function HOT 1
- Attribute error in parser
- parser error
- Unsized numbers without base solution
- Codegen arrays
- ANSI Style localparam causes parsing error
- TypeError: generate() got an unexpected keyword argument 'reorder' line 100 in Pyverilog/examples/example_graphgen.py
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