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Home Page: http://openasic.org/
License: Other
xkISP:Xinkai ISP IP Core (HLS)
Home Page: http://openasic.org/
License: Other
I'm using ubuntu22.04 with vivado_hls2021.1
when make in tcl some error catched like this:
/tools/Xilinx/Vitis_HLS/2021.1/include/mpfr.h:721:34: error: ‘mpfr_srcptr’ was not declared in this scope
__MPFR_DECLSPEC mpfr_exp_t mpfr_custom_get_exp _MPFR_PROTO ((mpfr_srcptr));
^~~~~~~~~~~
/tools/Xilinx/Vitis_HLS/2021.1/include/mpfr.h:725:28: error: ‘mpfr_srcptr’ was not declared in this scope
__MPFR_DECLSPEC int mpfr_custom_get_kind _MPFR_PROTO ((mpfr_srcptr));
^~~~~~~~~~~
In file included from /tools/Xilinx/Vitis_HLS/2021.1/include/hls_fpo.h:189:0,
from /tools/Xilinx/Vitis_HLS/2021.1/include/hls_half_fpo.h:64,
from /tools/Xilinx/Vitis_HLS/2021.1/include/hls_half.h:71,
from /tools/Xilinx/Vitis_HLS/2021.1/include/etc/ap_private.h:91,
from /tools/Xilinx/Vitis_HLS/2021.1/include/ap_common.h:653,
from /tools/Xilinx/Vitis_HLS/2021.1/include/ap_int.h:55,
from /home/yang/Documents/github/ISP/xkISP/tb/../src/top.h:19,
from /home/yang/Documents/github/ISP/xkISP/tb/../src/tpg.h:4,
from /home/yang/Documents/github/ISP/xkISP/tb/tb_tpg.cpp:1:
/tools/Xilinx/Vitis_HLS/2021.1/include/floating_point_v7_0_bitacc_cmodel.h:246:45: error: ‘mpfr_srcptr’ has not been declared
__XIP_FPO_DLL xip_fpo_exc_t xip_fpo_set_fr (xip_fpo_ptr, mpfr_srcptr);
^~~~~~~~~~~
/tools/Xilinx/Vitis_HLS/2021.1/include/floating_point_v7_0_bitacc_cmodel.h:247:53: error: ‘mpfr_srcptr’ has not been declared
__XIP_FPO_DLL xip_fpo_exc_t xip_fpo_fix_set_fr (xip_fpo_fix_ptr, mpfr_srcptr);
^~~~~~~~~~~
make[1]: *** [cosim.tv.mk:62: obj/tb_tpg.cpp_pre.cpp.tb.o] Error 1
ERROR: [COSIM 212-317] C++ compile error.
ERROR: [COSIM 212-321] EXE file generate failed.
ERROR: [COSIM 212-321] EXE file generate failed.
ERROR: [COSIM 212-331] Aborting co-simulation: C simulation failed, compilation errors.
ERROR: [COSIM 212-5] *** C/RTL co-simulation file generation failed. ***
ERROR: [COSIM 212-4] *** C/RTL co-simulation finished: FAIL ***
INFO: [HLS 200-111] Finished Command cosim_design CPU user time: 5.72 seconds. CPU system time: 0.46 seconds. Elapsed time: 6.2 seconds; current allocated memory: 375.555 MB.
command 'ap_source' returned error code
while executing
"source "./script.tcl""
(file "tpg.tcl" line 10)
invoked from within
"source tpg.tcl"
("uplevel" body line 1)
invoked from within
"uplevel \#0 [list source $arg] "
INFO: [HLS 200-112] Total CPU user time: 16.81 seconds. Total CPU system time: 1.63 seconds. Total elapsed time: 17.61 seconds; peak allocated memory: 373.383 MB.
INFO: [Common 17-206] Exiting vitis_hls at Mon Jun 27 23:19:59 2022...
make: *** [Makefile:13:tpg] 错误 1
I am using Ubuntu 20.04 and when I run isp executable in tv folder through the following command, it runs for a few seconds and then gives a segmentation fault.
./isp -i input.raw -c hls_param.txt
The error is shown below.
frame_width = 640
frame_height = 480
image_pattern = 3
blc = 0
noise_es_enable = 0
Img_Format = 2
Noise_Mode = 0
dgain_enable = 1
dgain_rgain = 16384
dgain_grgain = 16384
dgain_gbgain = 16384
dgain_dgain = 16384
lsc_enable = 1
lsc_config = 4
dpc_enable = 1
dpc_threshod_w = 300
dpc_threshod_b = 300
rawdns_enable = 1
rawdns_sigma = 30
rawdns_filter = 50
rawdns_bitwidth = 12
rawdnsParam.invksigma2 = 119
awb_enable = 0
awb_mink = 1
wbc_enable = 1
wbc_rgain = 4821
wbc_ggain = 4096
wbc_bgain = 6486
gb_enable = 1
ee_enable = 1
ee_coeff = 30
cmc_enable = 1
histeq_enable = 0
gtm_enable = 1
gtm_gamma = 1.200000
ltm_enable = 1
ltm_contrast = 3401
ltm_ratio = 38
cac_enable = 1
cac_t_transient = 7000
cac_t_edge = 4000
yuvdns_enable = 1
yuv_ysigma = 60
yuv_invysigma2 = 4
yuv_uvsigma = 80
yuv_invuvsigma2 = 2
ldc_enable = 0
output_yuvpattern = 0
output_times = 1
output_up = 0
output_left = 0
output_right = 640
output_down = 480
Segmentation fault (core dumped)
What could be the issue? Are there any GCC libraries that I am missing?
绿平衡模块算法有没有具体的原理,查找表和移位那一块看文档看的不是很懂
Hi, Sir;
May I get an FPGA board/Xilink from your support to verify the code in FPGA/Xlink Board?
Or I could upload your code into the Lattice FPGA board such as model No. is LIFCL-40-VIP-SI-PCBA.
Please give me your advice as soon as possible.
thanks
best regards
ben
你好,请问在LSC算法里的rgian等的值是怎么计算出来的,并且gian值数量是1317这和将图像划分为1216的方块有关系吗?
你好能提供下验证开发版嘛型号谢谢
/tv/isp,这个可执行文件的运行速度相当快,甚至包括了文件的读取和写入。可是自己编译产生的可执行文件,即使是单个模块运行速度也不快。我想问问项目里自带的isp是怎么得到的?
请问下isp.exe是怎么编译生成的谢谢
Run the catapullt script and get ERROR:
such as "cannot find ap_init.h / hls_stream.h"
I can convert ap_init.h to ac_init in catapult. But how to convert hls_stream.h ?
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