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flyingegret2018 avatar flyingegret2018 commented on September 10, 2024

We work on Xilinx Alevo U200/U250 with Vitis HLS flow. I think it needs some effort to upload to Lattice FPGA board.

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Benisonpin avatar Benisonpin commented on September 10, 2024

When can complete the Xilink Alevo U200U250 with Vitis HLS flow,
and may we get one from your site to verify, then return to you after verified?
thanks

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flyingegret2018 avatar flyingegret2018 commented on September 10, 2024

Please refer to README, the source files are in /fpga

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Benisonpin avatar Benisonpin commented on September 10, 2024

thanks for the reply
Is possible to put the code in the model of Xilinx xczu15eg?
can we have your hardware connecting drawing?
thanks again!

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Benisonpin avatar Benisonpin commented on September 10, 2024

Hi,sir:
is possible to put the source code in Xilinx xczu15eg with any effort?

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flyingegret2018 avatar flyingegret2018 commented on September 10, 2024

I think it's possible. We are also working on some similar Xilinx board.

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Benisonpin avatar Benisonpin commented on September 10, 2024

Hi, sir
thanks for your reply, would you please share with us about your current experience of implentation.
for example, may i got the Xilink board you had done?

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