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autobridge

[FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

axi-sdcard-high-speed-controller

A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)

aximm_to_axis

AXI-MM to AXI-Stream Conversion IP

axis_udp

This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supported. The project was tested on Xilinx 7-series FPGA with 10G Ethernet MAC IP-core

basic_verilog

Must-have verilog systemverilog modules

bayer2rgb

bayer2rgb with python

cdbus_ip

CDBUS Protocol and the IP Core for FPGA users

cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

core_dbg_bridge

UART -> AXI Bridge

core_ft60x_axi

FTDI FT600 SuperSpeed USB3.0 to AXI bus master

core_jpeg

High throughput JPEG decoder in Verilog for FPGA

directnvm

An open-source RTL NVMe controller IP for Xilinx FPGA.

dsp-rtl-lib

RTL Verilog library for various DSP modules

ebook-gpt-translator

Enjoy reading with your favorite style.

edalize

An abstraction library for interfacing EDA tools

eddr3

mirror of https://git.elphel.com/Elphel/eddr3

eth_vlg-1

fast-openisp

fast-openISP: a faster re-implementation of openISP

fpga-ftdi245fifo

FPGA-based USB fast data transmission using FT232H/FT600 chip. 使用FT232H/FT600芯片进行FPGA与电脑之间的高速数据传输。

fpga-network-stack

Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)

fpga-usb-device

An FPGA-based USB full-speed device core to implement USB-serial, USB-camera, USB-audio, USB-disk, USB-keyboard, etc. It requires 3 common IOs instead of additional chips. 基于FPGA的USB full-speed device端控制器，可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备，只需要3个FPGA普通IO，而不需要额外的接口芯片。

fpga_ip

OscillatorIMP ecosystem FPGA IP sources

fpgaandimage

image processing based FPGA

fpgaandlan

FPGAandLAN

fpgaandperipheralinterface

Peripheral Interface of FPGA

fpgahdl_xilinx

(RETIRED see https://github.com/analogdevicesinc/hdl instead) FPGA interface reference designs for Analog Devices mixed signal IC products

fpu

synthesiseable ieee 754 floating point library in verilog

freeahb

AHB Master

fusesoc

Package manager and build abstraction tool for FPGA/ASIC development