Shen's Projects
Implementation of an Adaptive Median Filter in Verilog (Simulation only)
Digilent's Arty S7-50 in Verilog 2001
AXI4 Interface Library
A DDR3 memory controller in Verilog for various FPGAs
Open source FPGA-based NIC and platform for in-network compute
Convolutional Neural Networks
A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
A collection of Master XDC files for Digilent FPGA and Zynq boards.
Library for fixed point arithmetic in C++
GigE Vision compatibe video streaming from MIPI-CSI camera with Zybo Z7-10 board
H264视频解码verilog实现
RTL, Cmodel, and testbench for NVDLA
iperf3: A TCP, UDP, and SCTP network bandwidth measurement tool
Little add-on to keep outlook running when clicking on exit
An open-source HEVC encoder
Linux Repository for digilent boards
Sample mmap code (utilizing kmalloc pages as "backing device")
A Linux kernel module that does network address translation
A kernel module to turn MASQUERADE into full cone SNAT
NetFPGA 1G infrastructure and gateware
Yilong's NetFPGA-10G Repo
Open Source H.264 Codec
Image Signal Processor
The PCI Utilities
progASICp4SWITCH
Config files for my GitHub profile.
Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator