[the initial issue has been solved, rx simulation is now working.]

Hi!

First I would like to express my appreciation for creating "openofdm", a complete SDR chain
that allows the translation of raw IQ data into bare 802.11 WiFi frames.

My name is Tobias and I am currently working on a NLnet funded project called "RA-Sentinel" [1]
in which I like using openwifi/openofdm as a core element to identify hacking attacks on WiFi networks.
For this purpose I need not only the raw WiFi frame content but also meta data, like frequency/phase offset
and maybe extra information taken out of the demodulator.

I am now on the way playing around with the dot11 module and simulation under Vivado.
I achieved porting the project to the latest Vivado 2024.1 which was not a hard task because
you documented the whole generation process really nicely. The simulation is working, now I am'
trying to get it running with my SDR hardware. (more details on gitub project page [1]).

Well I digged through your code, trying to find out how this all works in detail and barely found any
comments on wires and registers. I understand that your time was and still is limited of course.
So no worries I understand that you focussed on a reliably running code rather than explaining to
you obvious things in the code.

I would like to hear about your opinion adding more comments to improve readability. I would like to do this
by not change any of your code as such. Would that be something you would welcome and allow to check into
your existing code base our should I create a new, own fork?

B.t.w. I am also in contact with some other guy who would like to get rid of the AMD Viterbi decoder by replacing
it by a open source alternative. But this will come later, first I need to have the complete stack running
on the latest Vivado.

Best regards

Tobias

73 de DG3YEV

[1] https://github.com/Tobias-DG3YEV/RA-Sentinel

While doing my masters thesis, I came across the documentation for OpenOFDM. It states here (https://openofdm.readthedocs.io/en/latest/sig.html#fig-ht-sig) that the reserved bit should be 0, but according to the standard, it should be set to 1 (see 802.11n-2009 page 276). I could make a PR to fix this, but I don't know if there's any other place I should fix this in (the Verilog code maybe?)

Aside, I would really like to thank you for writing such clear documentation, it helped me a lot. Your blog post on the 802.11n CRC calculation in Python was also very useful, thank you!

Dear Jingshi,
I am a researcher from Ghent University, your open source project looks very interesting, and we'd like to test it on USRP N210. Though I am not able to synthesize successfully. Could you help me with it? Below is a few details:

I followed your instruction in "Integration with USRP", modified the Makefile.N210R4 into a customized version, added the Verilog macro, but instead of commenting out the CUSTOM_SRC, I used it to specify the custom_dsp_rx.v file, I could compile a bitstream for N210 successfully at this point

Then I instantiated dot11.v module in custom_dsp_rx.v, and also added the verilog files listed in dot11_modules.list in the CUSTOM_SRC, after this the compilation fails and complaining some unresolved names. I checked that all of them are the ones with Xilinx cores.

As a 3rd step I tried to add ngc files of the Xilinx cores located in the openofdm/verilog/coregen folder. Though then Xilinx ISE12.2 compiler seems to enter a deadlock status, and never finishes the compilation.

So help me to find what is the correct way of adding the source file with Xilinx cores to the usrp2 project?

Thank you in advance,
Wei

您好！请问一下解码部分从解调制到解交织，软解码的思路和逻辑，能不能指点一下，是怎么根据相应的判断条件来确定out_bits的值的，如果能细致解答一下真的万分感谢，这里的思路没看懂很苦恼，如果看到了这条消息希望能解答一下疑惑，万分感谢！

Anyone succeeds simulating this project using iverilog?

I have captured the IQ data of wifi transmitter by USRP B210.

Is this available for the IQ data captured from USRP B210?

The link between compilation and simulation tutorials is not found. Is there a new link that can be posted

First, thanks a lot for this cool project!

During some initial tests with the code base, i run into the following issue, which seems to be a bug:

I run the test.py script with your sample from https://openofdm.readthedocs.io/en/latest/_downloads/samples.dat using the following command: python2 test.py samples.dat --no_sim

I am running the script on a Ubuntu 20.04 LTS, x86_64 system and end up with an out of range error. Below, you can find the log:

andreas@dev-pc:~/mnt/hdd1/openofdm/scripts$ python2 test.py samples.dat --no_sim
Using file /home/andreas/mnt/hdd1/openofdm/scripts/samples.dat (21440 samples)
Decoding...
Power trigger at 0
Decoding packet starting from sample 11
[COARSE OFFSET] 0.010686 (2)
[FINE OFFSET] 0.000318 (0)
[FREQ OFFSET] 0.010686 (2)
[PILOT OFFSET] 0.016022 (4)
[NO PUNCTURE]
[SIGNAL] {'parity_bits': '1', 'len_bits': '010100010000', 'rsvd': '0', 'length': 138, 'ht': False, 'tail_bits': '000000', 'rate': 24, 'parity_ok': True, 'rate_bits': '1001', 'mcs': 0}
12 DATA OFDM symbols to decode
[PILOT OFFSET] 0.086909 (22)
[PILOT OFFSET] 0.110029 (28)
[PILOT OFFSET] 0.104411 (26)
[PILOT OFFSET] 0.133532 (34)
[PILOT OFFSET] 0.205433 (52)
[PILOT OFFSET] 0.227036 (58)
[PILOT OFFSET] 0.255751 (65)
[PILOT OFFSET] 0.279896 (71)
[PILOT OFFSET] 0.312476 (79)
[PILOT OFFSET] 0.349655 (89)
[PILOT OFFSET] 0.362203 (92)
[PILOT OFFSET] 0.392154 (100)
[NO PUNCTURE]
[  0] 88 42 2c 00 e4 90 7e 15 2a 16 e8 de 27 90 6e 42
[ 16] e8 de 27 90 6e 40 70 13 00 00 05 01 00 20 00 00
[ 32] 00 00 43 e0 7b 59 2e 77 13 34 95 a7 85 f5 32 69
[ 48] 08 38 4f c5 99 0f ea a6 13 c4 ee df f7 22 e2 fe
[ 64] 34 7d 75 95 f3 74 45 f5 1a 33 18 bb 8b 02 53 ed
[ 80] dc e9 74 28 b7 08 33 04 82 fc a2 f5 72 ac 8f 87
[ 96] 99 8f 22 64 79 62 ac f9 9d 38 3d ed 8c c4 bc 95
[112] ce ed da 08 cc 1d a2 d2 39 07 9b 0a 43 2f 4c f4
[128] ad 61 5b 2a dc 7c 52 7f 21 e9
Stop after 1640 samples
Traceback (most recent call last):
  File "test.py", line 217, in <module>
    test()
  File "test.py", line 97, in test
    if getattr(expected_signal, attr) == signal_out[idx]:
IndexError: list index out of range

I noticed in the do_mult task the first stage of the correlation has the terms (sync_long.v, lines 467-470):

stage_X0 <= cross_corr_buf[1];
stage_X1 <= cross_corr_buf[2];
stage_X2 <= cross_corr_buf[3];
stage_X3 <= cross_corr_buf[4];

I believe the indexing should start be [0:3]. This would also be consistent with the 2nd, 3rd and 4th stages of the cross correlation.

Hi
i have doubt that can i simulate complete design on modelsim?
regards
hyanki

I find the file power_trigger.v line 57 ,the abs_i is the complement code of input_i,Why were you called the signal name is abs_i? the abs_i means absolute value.

always @(posedge clock) begin
    if (reset) begin
        sample_count <= 0;
        trigger <= 0;
        abs_i <= 0;
        state <= S_SKIP;
    end else if (enable & sample_in_strobe) begin
        abs_i <= input_i[15]? ~input_i+1: input_i;
        case(state)
            S_SKIP: begin
                if(sample_count > num_sample_to_skip) begin
                    state <= S_IDLE;
                end else begin
                    sample_count <= sample_count + 1;
                end
            end

            S_IDLE: begin
                if (num_sample_changed) begin
                    sample_count <= 0;
                    state <= S_SKIP;
                end else if (abs_i > power_thres) begin
                    // trigger on any significant signal 
                    trigger <= 1;
                    sample_count <= 0;
                    state <= S_PACKET;
                end
            end

            S_PACKET: begin
                if (num_sample_changed) begin
                    sample_count <= 0;
                    state <= S_SKIP;
                end else if (abs_i < power_thres) begin
                    // go back to idle for N consecutive low signals
                    if (sample_count > window_size) begin
                        trigger <= 0;
                        state <= S_IDLE;
                    end else begin
                        sample_count <= sample_count + 1;
                    end
                end else begin
                    sample_count <= 0;
                end
            end
        endcase
    end
end
endmodule

Why adds 4 clock delay in the data inputs of rotate.v?
one delayT module with 4 clock delay for data and one delayT module with 4 clock delay for the strobe.
Thank.

Best regards

Jinsan Ko