Comments (5)
@bby0616 Yes, I did. However, since there has been no activity here so far, I haven't PRd it back to this repo. I upgraded the script to python3 (including many additional adjustment. Feel free to have a look/fork it from here: https://github.com/andreaskuster/openofdm
Thanks bro, I am really appreciate your help
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Have you tried the dot11zynq branch?
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@JiaoXianjun Assuming you are referring to the dot11zynq
branch from the opensdr
fork (here) , i can confirm that the error is present there as well.
Btw: Which is your actual development repo? Is it this (https://github.com/jhshi/openofdm) or the one in opensdr (https://github.com/open-sdr/openofdm) ?
I am asking since I am porting this library to the Ettus B210 device and will eventually open a PR..
from openofdm.
@JiaoXianjun Assuming you are referring to the
dot11zynq
branch from theopensdr
fork (here) , i can confirm that the error is present there as well.Btw: Which is your actual development repo? Is it this (https://github.com/jhshi/openofdm) or the one in opensdr (https://github.com/open-sdr/openofdm) ? I am asking since I am porting this library to the Ettus B210 device and will eventually open a PR..
have you ever solved this problem? I have faced the same trouble with you
from openofdm.
@bby0616 Yes, I did. However, since there has been no activity here so far, I haven't PRd it back to this repo. I upgraded the script to python3 (including many additional adjustment. Feel free to have a look/fork it from here: https://github.com/andreaskuster/openofdm
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Related Issues (16)
- rotate.v has 9 clock delay
- incorrect indexing in sync_long.v HOT 1
- testing on USRP HOT 2
- Simulation enviorment set up
- Reserved bit in 802.11n should be 1 (instead of 0) HOT 1
- The included openofdm_rx_pre_def.v modules isn't om the repository HOT 1
- The included module openofdm_rx_pre_def.v is missing please provide a solution HOT 1
- is there any other implementation of 802.11 ofdm decoder in verilog avaliable or corrected version of the current repo please provide a solution HOT 1
- How to compile and simulate
- Simulation of power trigger module
- 解码部分代码逻辑问题
- Simulation in Vivado 2024.1 stuck at state 3 S_DECODE_SIGNAL
- abs_i name
- Is this available for the IQ data captured from USRP B210? HOT 1
- Simulation of full HDL HOT 3
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