spinalhdl / naxriscv Goto Github PK

With the SpinalHDL version being a dependency of Nax, it should be included as a git submodule. Or we are left wondering what version will work.

From Nax root folder :

git submodule add https://github.com/SpinalHDL/SpinalHDL.git SpinalHDL

Alter build.sbt:

// SPDX-FileCopyrightText: 2023 "Everybody"
//
// SPDX-License-Identifier: MIT

val spinalVersion = "dev"
val spinalhdl_path = (new java.io.File(".")).getCanonicalPath + "/SpinalHDL"

lazy val root = (project in file(".")).
  settings(
    inThisBuild(List(
      organization := "com.github.spinalhdl",
      scalaVersion := "2.11.12",
      version      := "2.0.0"
    )),
    scalacOptions +=  s"-Xplugin:${new File(spinalhdl_path + s"/idslplugin/target/scala-2.11/spinalhdl-idsl-plugin_2.11-$spinalVersion.jar")}",
    scalacOptions += s"-Xplugin-require:idsl-plugin",
    libraryDependencies ++= Seq(
      "org.scalatest" %% "scalatest" % "3.2.5",
      "org.yaml" % "snakeyaml" % "1.8",
      "net.fornwall" % "jelf" % "0.7.0"
    ),
    Compile / unmanagedSourceDirectories += baseDirectory.value / "ext/rvls/bindings/jni",
    name := "NaxRiscv"
  ).dependsOn(spinalHdlIdslPlugin, spinalHdlSim,spinalHdlCore,spinalHdlLib)
lazy val spinalHdlIdslPlugin = ProjectRef(file(spinalhdl_path), "idslplugin")
lazy val spinalHdlSim = ProjectRef(file(spinalhdl_path), "sim")
lazy val spinalHdlCore = ProjectRef(file(spinalhdl_path), "core")
lazy val spinalHdlLib = ProjectRef(file(spinalhdl_path), "lib")

fork := true

Hi,

Does NAX or Vex have a Core Local Interrupt (CLINT) controller? It provides timer interrupts and inter-core interrupt mechanisms (IPIs) at the per-core level.

Here's a brief overview of how the mtime CSR and the software interrupt mechanism work within the context of the CLINT:

mtime CSR (Machine Timer Counter): The mtime CSR is a machine-level CSR that represents a timer or counter. It is often used for timing and scheduling purposes. Each core (hart) in a multi-core RISC-V processor typically has its own mtime CSR, which can be read and updated independently. The mtime CSR can be used for various purposes, including tracking time and generating timer interrupts.

Timer Interrupts: The mtime CSR can be programmed to generate timer interrupts at specific intervals. When the mtime CSR reaches a particular value (usually compared against a threshold), it triggers a timer interrupt. This interrupt can be used for tasks like preemptive multitasking, where the processor switches between different tasks when a timer interrupt occurs.

Software-Managed Interrupt Bit (MSIP): Besides timer interrupts, the CLINT also provides a software-managed interrupt bit known as MSIP (Machine Software Interrupt Pending). Each core has its own MSIP bit, which can be set or cleared by software running on that core. This software interrupt mechanism is often used for inter-core communication or coordination. When one core wants to notify another core of an event or task, it can set the MSIP bit of the target core.

Inter-Core Interrupts (IPIs): The software-managed MSIP bit can implement inter-core interrupts or IPIs. When a core sets the MSIP bit of another core, it signals the target core to handle the interrupt and execute a specific software handler. This mechanism is helpful for communication between cores in a multi-core system.

Hi^^
I want to build a project with NaxRiscv.I refer to existing works(LiteX and single core generation), and I build a soc like this, with my qspi controller and uart:

class NaxSoc() extends Component {
    val io = new Bundle {
        val debug        = slave(Jtag())
        val debug_resetn = in Bool ()
        val uart         = master(Uart())
        val qspi         = master(Qspi())
    }
    private def priv_port(cpu: NaxRiscv)        = cpu.framework.getService[PrivilegedPlugin].io
    def int_mtimer(cpu: NaxRiscv)               = priv_port(cpu).int.machine.timer
    def int_msoftware(cpu: NaxRiscv)            = priv_port(cpu).int.machine.software
    def int_mexternal(cpu: NaxRiscv)            = priv_port(cpu).int.machine.external
    def int_sexternal(cpu: NaxRiscv)            = priv_port(cpu).int.supervisor.external
    def int_rdtime(cpu: NaxRiscv)               = priv_port(cpu).rdtime
    def dbg_jtag(cpu: NaxRiscv)                 = cpu.framework.getService[EmbeddedJtagPlugin].logic.jtag
//FetchAxi4Parrot split a single axi4 to double axi4, modified from FetchAxi4 plugin
    def inst_main(cpu: NaxRiscv)                = cpu.framework.getService[FetchAxi4Parrot].logic.axiRam
    def inst_perp(cpu: NaxRiscv)                = cpu.framework.getService[FetchAxi4Parrot].logic.axiPeripheral
    def data_ram(cpu: NaxRiscv)                 = cpu.framework.getService[DataCacheAxi4].logic.axi
    def data_perp(cpu: NaxRiscv)                = cpu.framework.getService[LsuPeripheralAxi4].logic.axi

    io.debug.setName("jtag")
    io.uart.setName("uart")
    io.qspi.setName("qspi")
    io.debug_resetn.setName("jtag_rstn")
    val core_cfg = initCfg(
      resetVector = 0x00000000L,
      ioRange = _(31 downto 28) === 0x2,
      fetchRange = _(31 downto 28) =/= 0x2
    )
    core_cfg.foreach {
        case p: EmbeddedJtagPlugin => p.debugCd.load(ClockDomain.current.copy(reset = io.debug_resetn))
        case _                     =>
    }
    val core = new NaxRiscv(core_cfg)

    Axi4SpecRenamer(inst_main(core))
    Axi4SpecRenamer(data_ram(core))
    Axi4SpecRenamer(inst_perp(core))
    Axi4SpecRenamer(data_perp(core))

    io.debug <> dbg_jtag(core)

//Just for test, set all INT to zero
    int_mtimer(core).clear()
    int_msoftware(core).clear()
    int_mexternal(core).clear()
    int_sexternal(core).clear()
    int_rdtime(core).clearAll()
//A qspi controller with two port,axi4 for reading(at address mapping mode,but read only),axilite4 for config and writing
    val qspi_flash = new myQspiTop(
      inst_port_cfg = Axi4Config(addressWidth = 32, dataWidth = 64, idWidth = 2),
      perp_port_cfg = AxiLite4Config(addressWidth = 32, dataWidth = 32)
    )

    val qspi_flash_perp = Axi4(Axi4Config(addressWidth = 32, dataWidth = 32, idWidth = 1))
    qspi_flash.io.perp_port << qspi_flash_perp.toLite

    val ram = new Axi4SharedOnChipRam(dataWidth = 64, byteCount = 256, idWidth = 2, arwStage = true)

    val main_bus = Axi4CrossbarFactory()
    main_bus.addSlaves(
      ram.io.axi -> (0x10000000L,16 MiB)
    )
    main_bus.addConnections(
        inst_main(core) -> List(ram.io.axi),
        data_ram(core) -> List(ram.io.axi)
    )
    main_bus.build()
    val perp_stor_bus = Axi4CrossbarFactory()
    perp_stor_bus.addSlaves(
        qspi_flash.io.inst_port -> (0x00000000L, 16 MiB)
    )
    perp_stor_bus.addConnections(
      inst_perp(core) -> List(qspi_flash.io.inst_port)
    )
    perp_stor_bus.build()

//A simple uart controller with apb bus
    val uart            = new myUartCore()
    val uart_apb_master = Apb3(5, 32)
//Just change the datawidth from 32 to 8,nothing else
    resizeConnect(slave = uart.io.apb, master = uart_apb_master)

    val perpApb = Axi4SharedToApb3Bridge(
      addressWidth = 20,
      dataWidth = 32,
      idWidth = 1
    )
    val perp_bus = Axi4CrossbarFactory()
    perp_bus.addSlaves(
      qspi_flash_perp -> (0x50000000L, 1 KiB),
      perpApb.io.axi  -> (0x20000000L, 16 KiB)
    )
    perp_bus.addConnections(
      data_perp(core) -> List(qspi_flash_perp, perpApb.io.axi)
    )
    perp_bus.build()
    val apbDecoder = Apb3Decoder(
      master = perpApb.io.apb,
      slaves = List(
        uart_apb_master -> (0x00000, 4 KiB)
      )
    )
    io.uart <> uart.io.uart
    io.qspi <> qspi_flash.io.qspi
}

I tried to simulate it in IVerilog with these code:

object socTest extends App {
//A code to load bin file for qspi flash model,and it works well i think.
    val qspi_file = qspiRedirect.startSim("../../bin/test.bin")
    class sim_soc extends Component {
        val io = new Bundle {
            val debug        = slave(Jtag())
            val debug_resetn = in Bool ()
            val uart         = master(Uart())
        }
        val soc = new NaxSoc()
        soc.io.debug <> io.debug
        soc.io.debug_resetn <> io.debug_resetn
        soc.io.uart <> io.uart

        val qspi_flash = new qspiModel

        soc.io.qspi.csn <> qspi_flash.io.CSn
        soc.io.qspi.sck <> qspi_flash.io.CLK

        soc.io.qspi.dout(0) <> qspi_flash.io.DIO.write
        soc.io.qspi.dout(1) <> qspi_flash.io.DO.write
        soc.io.qspi.dout(2) <> qspi_flash.io.WPn.write
        soc.io.qspi.dout(3) <> qspi_flash.io.HOLDn.write

        soc.io.qspi.dout_en(0) <> qspi_flash.io.DIO.writeEnable
        soc.io.qspi.dout_en(1) <> qspi_flash.io.DO.writeEnable
        soc.io.qspi.dout_en(2) <> qspi_flash.io.WPn.writeEnable
        soc.io.qspi.dout_en(3) <> qspi_flash.io.HOLDn.writeEnable

        soc.io.qspi.din(0) <> qspi_flash.io.DIO.read
        soc.io.qspi.din(1) <> qspi_flash.io.DO.read
        soc.io.qspi.din(2) <> qspi_flash.io.WPn.read
        soc.io.qspi.din(3) <> qspi_flash.io.HOLDn.read
    }
    def simCfg = {
        val cfg = SpinalConfig(
          nameWhenByFile = true,
          inlineRom = true,
          targetDirectory = "./gen",
          defaultConfigForClockDomains = ClockDomainConfig(resetActiveLevel = LOW)
        )
        cfg.addTransformationPhase(new MemReadDuringWriteHazardPhase)
        cfg.addTransformationPhase(new MemReadDuringWritePatcherPhase)
        cfg.addTransformationPhase(new MultiPortWritesSymplifier)
        cfg
    }
   SimConfig.withConfig(spinal).withIVerilog.withWave.compile(new sim_soc).doSimUntilVoid { dut =>
        dut.clockDomain.forkStimulus(period = 10000)
        SimTimeout(10000*100000)
    }
}

I don't know if there're any errors in these code, but it could not work in simulation, fetchcache read two line, and dead. At first, I think it's the fault of the code. But I can simulate the code well just with the single Nax core(copy the verilog code to a questasim project and simulate with systemverilog).and I add a line in the simCfg:cfg.includeSimulation.Ok, with this command, fetchcache read four line!(and dead). Both of them have no response on datacache and lsu port, their addr ports are always X.

So my problem is:

1. Is there any problem with the soc I build and simulation project?What problems could they have?
2. For includeSimulation and its cousins includeSynthesis ,what kind of roles do they play in this project and spinalhdl?

Thanks for your help!

Hi !
Do you have any plans about implement the the whole soc (with spi，uart) , which can boot the linux simulation and show results from the uart?

Dear charles,

How you recommend me to compile the updated code with

sbt "runMain naxriscv.Gen64"

like which branch to stay in spinal HDL and which branch to stay in main one ?

hsubedi@kronos:~/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/naxRiscv_recurisve$ l
assets/  build.sbt  ext/  LICENSES/  project/  README.md  reuse.sh*  src/  target/

hsubedi@kronos:~/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/naxRiscv_recurisve$ cd ext/
NaxSoftware/    riscv-isa-sim/  rvls/           SpinalHDL/      SpinalHDL_orig/ 

hsubedi@kronos:~/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/naxRiscv_recurisve$ cd ext/SpinalHDL

hsubedi@kronos:~/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/naxRiscv_recurisve/ext/SpinalHDL$ l
build.sbt  build.sc  cocotbWorkspace/  CONTRIBUTING.md  core/  idslpayload/  idslplugin/  lib/  LICENSE  LICENSE_core  LICENSE_lib  project/  README.md  scalaplugin/  scala.yml  sim/  tester/  tools.sh

hsubedi@kronos:~/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/naxRiscv_recurisve/ext/SpinalHDL$ git branch -a
* dev
 master
 naxriscv
 remotes/origin/HEAD -> origin/dev
 remotes/origin/PhaseCheckCrossClock-fix
 remotes/origin/async
 remotes/origin/bmbl2cache
 remotes/origin/bus-fabric
 remotes/origin/commentRtlEntity
 remotes/origin/compiler_plugin_2.12
 remotes/origin/contributor-guide
 remotes/origin/def_1.6.2
 remotes/origin/dev
 remotes/origin/dma_fix
 remotes/origin/dolu
 remotes/origin/enum-merge
 remotes/origin/fifo-rework
 remotes/origin/fix-cc-meta
 remotes/origin/funding-yaml-1
 remotes/origin/gh-pages
 remotes/origin/inout-fix
 remotes/origin/master
 remotes/origin/naxriscv
 remotes/origin/naxriscv_backup
 remotes/origin/pcie
 remotes/origin/riscv-debug
 remotes/origin/scala3
 remotes/origin/scala3-dev
 remotes/origin/scala_2.12
 remotes/origin/scala_2.12_dev
 remotes/origin/scala_2.13
 remotes/origin/scala_2.13_dev
 remotes/origin/snoopy
 remotes/origin/soc_fmax
 remotes/origin/tilelink
 remotes/origin/tilelink-l2
hsubedi@kronos:~/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/naxRiscv_recurisve/ext/SpinalHDL$ cd ..
hsubedi@kronos:~/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/naxRiscv_recurisve/ext$ cd ..
hsubedi@kronos:~/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/naxRiscv_recurisve$ git branch -a
* main
 remotes/origin/HEAD -> origin/main
 remotes/origin/asic
 remotes/origin/cleaning
 remotes/origin/coherency
 remotes/origin/dev
 remotes/origin/fast-reschedule
 remotes/origin/fix_fetch_cache_plugin_mem_rsp_ready
 remotes/origin/fpu
 remotes/origin/jtag
 remotes/origin/lsu2
 remotes/origin/lsu_peripheral_store_cmd_ahead
 remotes/origin/main
 remotes/origin/reuse_licenses
 remotes/origin/riscv-debug

I get following errors

hsubedi@kronos:~/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/naxRiscv_recurisve$ sbt "runMain naxriscv.Gen64"
[info] welcome to sbt 1.6.0 (Amazon.com Inc. Java 11.0.20.1)
[info] loading settings for project naxriscv_recurisve-build from plugins.sbt ...
[info] loading project definition from /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/naxRiscv_recurisve/project
[info] loading settings for project root from build.sbt ...
[info] loading settings for project spinalhdl-build from plugin.sbt ...
[info] loading project definition from /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/naxRiscv_recurisve/ext/SpinalHDL/project
[info] loading settings for project all from build.sbt ...
[info] set current project to NaxRiscv (in build file:/home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/naxRiscv_recurisve/)
[info] compiling 125 Scala sources and 3 Java sources to /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/naxRiscv_recurisve/target/scala-2.11/classes ...
[error] /home/hsubedi/instruction_test_bed/riscv_NAX_2_l2_cache_new_pull/naxRiscv_recurisve/src/main/scala/naxriscv/platform/litex/NaxSoc.scala:45:38: not found: type ResetCtrlFiber
[error]   val socResetCtrl = socClkCd on new ResetCtrlFiber().addAsyncReset(asyncReset, HIGH)
[error]                                      ^
[error] one error found
[error] (Compile / compileIncremental) Compilation failed
[error] Total time: 17 s, completed Oct 26, 2023, 11:26:03 PM

Error while compiling new nax in litex:

Another error while compiling Updated nax in litex is following

Updated

hsubedi@kronos:~/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/ext$ git clone --recursive https://github.com/SpinalHDL/NaxRiscv.git

hsubedi@kronos:~/instruction_test_bed/litex/fpga_nax_3$ python3 -m litex_boards.targets.digilent_arty --variant a7-100           --cpu-type naxriscv --xlen 64 --cpu-count 1 --l2-bytes 0           --update-repo no --build

Errors are such

 NaxRiscv netlist : NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009
NaxRiscv generation command :
cd /home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/ext/NaxRiscv && sbt "runMain naxriscv.platform.litex.NaxGen --netlist-name=NaxRiscvLitex_c93d54487019bd02d4c497a6f16e6009 --netlist-directory=/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog --reset-vector=0 --xlen=64 --cpu-count=1 --l2-bytes=4096 --l2-ways=8 --litedram-width=128 --memory-region=2147483648,2147483648,io,p --memory-region=0,131072,rxc,p --memory-region=268435456,8192,rwxc,p --memory-region=1073741824,268435456,rwxc,m --memory-region=4026531840,65536,rw,p --scala-file=/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/configs/gen.scala"
[info] welcome to sbt 1.6.0 (Amazon.com Inc. Java 11.0.20.1)
[info] loading settings for project naxriscv-build from plugins.sbt ...
[info] loading project definition from /home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/ext/NaxRiscv/project
[info] loading settings for project root from build.sbt ...
[info] loading settings for project spinalhdl-build from plugin.sbt ...
[info] loading project definition from /home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/ext/NaxRiscv/ext/SpinalHDL/project
[info] loading settings for project all from build.sbt ...
[info] set current project to NaxRiscv (in build file:/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/ext/NaxRiscv/)
[info] compiling 125 Scala sources and 3 Java sources to /home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/ext/NaxRiscv/target/scala-2.11/classes ...







[info] compiling 125 Scala sources and 3 Java sources to /home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/ext/NaxRiscv/target/scala-2.11/classes ...
[error] /home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/ext/NaxRiscv/src/main/scala/naxriscv/platform/tilelinkdemo/SocSim.scala:8:8: object ScopeFiber is not a member of package spinal.lib.bus.tilelink
[error] import spinal.lib.bus.tilelink.ScopeFiber
[error]        ^
[error] /home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/ext/NaxRiscv/src/main/scala/naxriscv/platform/tilelinkdemo/SocSim.scala:93:21: not found: type ScopeFiber
[error]     val scope = new ScopeFiber()
[error]                     ^
[error] two errors found
[error] (Compile / compileIncremental) Compilation failed
[error] Total time: 82 s (01:22), completed Oct 26, 2023, 11:55:29 PM
Traceback (most recent call last):
File "/usr/lib/python3.10/runpy.py", line 196, in _run_module_as_main
  return _run_code(code, main_globals, None,
File "/usr/lib/python3.10/runpy.py", line 86, in _run_code
  exec(code, run_globals)
File "/home/hsubedi/instruction_test_bed/litex/litex-install/litex-boards/litex_boards/targets/digilent_arty.py", line 221, in <module>
  main()
File "/home/hsubedi/instruction_test_bed/litex/litex-install/litex-boards/litex_boards/targets/digilent_arty.py", line 210, in main
  builder.build(**parser.toolchain_argdict)
File "/home/hsubedi/instruction_test_bed/litex/litex-install/litex/litex/soc/integration/builder.py", line 332, in build
  self.soc.finalize()
File "/home/hsubedi/instruction_test_bed/litex/litex-install/litex/litex/soc/integration/soc.py", line 1311, in finalize
  Module.finalize(self)
File "/home/hsubedi/instruction_test_bed/litex/litex-install/migen/migen/fhdl/module.py", line 156, in finalize
  subfragments = self._collect_submodules()
File "/home/hsubedi/instruction_test_bed/litex/litex-install/migen/migen/fhdl/module.py", line 149, in _collect_submodules
  r.append((name, submodule.get_fragment()))
File "/home/hsubedi/instruction_test_bed/litex/litex-install/migen/migen/fhdl/module.py", line 102, in get_fragment
  self.finalize()
File "/home/hsubedi/instruction_test_bed/litex/litex-install/migen/migen/fhdl/module.py", line 157, in finalize
  self.do_finalize(*args, **kwargs)
File "/home/hsubedi/instruction_test_bed/litex/litex-install/litex/litex/soc/cores/cpu/naxriscv/core.py", line 523, in do_finalize
  self.add_sources(self.platform)
File "/home/hsubedi/instruction_test_bed/litex/litex-install/litex/litex/soc/cores/cpu/naxriscv/core.py", line 351, in add_sources
  self.generate_netlist(self.reset_address)
File "/home/hsubedi/instruction_test_bed/litex/litex-install/litex/litex/soc/cores/cpu/naxriscv/core.py", line 343, in generate_netlist
  subprocess.check_call(cmd, shell=True)
File "/usr/lib/python3.10/subprocess.py", line 369, in check_call
  raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command 'cd /home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/ext/NaxRiscv && sbt "runMain naxriscv.platform.litex.NaxGen --netlist-name=NaxRiscvLitex_8e17be2040cf5cba55f37a79ee56b236 --netlist-directory=/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog --reset-vector=0 --xlen=64 --cpu-count=1 --l2-bytes=0 --l2-ways=8 --litedram-width=128 --memory-region=2147483648,2147483648,io,p --memory-region=0,131072,rxc,p --memory-region=268435456,8192,rwxc,p --memory-region=1073741824,268435456,rwxc,m --memory-region=4026531840,65536,rw,p --scala-file=/home/hsubedi/instruction_test_bed/litex/litex-install/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/configs/gen.scala"' returned non-zero exit status 1.

Hi,
I wanted to ask how much amount of work it will be to extend the NaxRiscv with a few custom instructions for AI, for instance, vector-matrix multiply? Thanks.

I wrote the firmware in rust code with read function, I tried to run this program in Naxriscv but stuck in read function.

Another side, I tried that function in vexriscv ,this worked fine!

This is the firmware:
unsafe fn main() -> ! {
// led debug
let LED_ADDR: u32 = 0x10000000;//0x10000000 with vexrisc and 0xFF000000 with naxrisc
let mut led: u32 = 0x00000000;
//let mut tcp_status;

// TCP interface
//let TCP_STATUS_ADDR: u32 = 0xFF000000;
//let TCP_RX_ADDR: u32 = 0xff000020;
//let TCP_TX_ADDR: u32 = 0xff000030;

// init led
(LED_ADDR as *mut u32).write_volatile(led);
loop {
   led = (LED_ADDR as *mut u32).read();
   
   led = led ^ 0xFFFF000;
    (LED_ADDR as *mut u32).write_volatile(led);
    
    delay(100);
}

}

Can you please check that?

Thank you,
Duc

Are there plans to add TAGE Branch Predictor as a plugin in the future?

Hi, The NaxRiscv project is really great!
I am learning a lot about testing hardware designs from this project.

An error like *** MISSMATCH PC DUT=8000000c REF=0 *** occurred when a program containing an illegal memory access was executed by verilator. Is this an expected behavior? If the post-processing due to illegal memory accesses is matched with spike, I would expect the RTL and spike behavior to match. What could be the cause?

Reproduction steps:

1. Prepare the following assembly file in NaxSoftware's bare metal environment. The file path is /NaxRiscv/ext/NaxSoftware/baremetal/test/crt.S.

.globl _start
_start:
    addi x1, x1, 64
    addi x2, x2, 64
    sw x3, 0(x0)
    ret

2. Compile with command make -C $NAXRISCV/ext/NaxSoftware/baremetal/test RISCV_PATH=$RISCV MARCH=rv32im MABI=ilp32.
3. Execute with command cd $NAXRISCV/src/test/cpp/naxriscv; ./obj_dir/VNaxRiscv --load-elf ../../../../ext/NaxSoftware/baremetal/test/build/test.elf.
4. The following output is generated.

*** MISSMATCH PC DUT=8000000c REF=0 ***

TIME=262
LAST PC COMMIT=8000000c
INCOMING SPIKE PC=0
ROB_ID=x5
FAILURE ???

Dear Dolu1990
The Nax project is really great!
Its software architecture is very helpful for learning and research, and it also has great application prospects in engineering implementation. I sincerely hope that this architecture can become popular among developers like LazyModule in chisel.

So far, I have been learning Nax for almost half a year, but I have only touched a little bit, and it is still a little far from engineering applications.
I hope to be familiar with Nax's development process as soon as possible and use it in product development.

The requirements of my project are as follows. Input instructions through the Fifo interface or FetchCachePlugin_mem interface (no branch prediction is required), and then through instruction decoding, instruction dispatch, instruction execution, instruction reordering, instruction commit, instruction writeback and other operations, the instruction result will be Storage FIFO or RAM.

I would like to be able to reuse most of the Nax code and be able to implement a user-defined instruction set.

I have been fumbling with ExecuteUnitBase and ExecuteUnitDemo for a few days, and probably understand the relevant code, but it feels very difficult to modify ExecuteUnit according to the needs, and, so far, I can't integrate ExecuteUnitDemo into Gen (it seems that I need to write an extended subclass) .

https://github.com/SpinalHDL/NaxRiscv/blob/main/src/main/scala/naxriscv/execute/ExecuteUnitDemo.scala
https://github.com/SpinalHDL/NaxRiscv/blob/main/src/main/scala/naxriscv/Gen.scala

@Dolu1990
Can you have a simple demo code of the whole process (including: decoding, encoding, integration and bare metal testing of custom operators), which can enable us beginners to apply engineering as soon as possible.

Also, do we have plans to implement riscv vector instruction extensions? Or just implement a framework, what do you think?

Best regards！

There are hints for getting the linux-on-litex image working by modifying the dts/dtb.
I am unsure what needs to be done.
Would it be possible to get some more instructions for this?

Hello,

I'm trying to understand how the NaxRiscV design handles CPU read/write requests and how they are distributed among FetchCachePlugin, LsuPlugin, and DataCachePlugin. However, I'm finding it difficult to navigate through the code due to the large number of internal signals and connections.

Can you please provide more details on how the control logic within the processor identifies and routes these requests to the appropriate plugins? Additionally, I would greatly appreciate any guidance on understanding the code structure and where to focus my attention while analyzing the internal signals and connections.

From my understanding:

1. FetchCachePlugin is responsible for fetching instructions from memory based on the program counter's address request.
2. LsuPlugin handles data transfers between the processor and peripherals when executing I/O operations (e.g., reading/writing GPIO, UART, SPI, etc.).
3. DataCachePlugin manages data read/write operations between the processor and the data cache for memory access (e.g., accessing variables in memory).

How does the processor's control logic route the read/write requests to the correct plugin, based on instruction type and operands?

I've also noticed that there are configuration items, such as ioRange and fetchRange, in the Gen.scala file. Could you please explain their purpose and how they affect the processor's behavior?

Any clarification, examples, or guidance on navigating the code would be greatly appreciated.

Thank you for your help!

I tried

python3 -m litex_boards.targets.digilent_nexys_video --cpu-type=naxriscv --with-video-framebuffer --with-sdcard --build --load

but i get this error

OSError: Unable to find or source Vivado toolchain, please either:

• Source Vivado's settings manually.
• Or set LITEX_ENV_VIVADO environment variant to Vivado's settings path.
• Or add Vivado toolchain to your $PATH.

Do you know how to solve this issue with finding or sourcing the Vivado toolchain for my project.

Hi,
I just bought a digilent nexsys video FPGA card and run step -by step to boot Linux according which NaxRiscv document desicribed.
I can boot !!! and login from uart terminal.
But for HDMI output , It just shows a login prompt:

"Debian GNU/Linux bookworm/sid sid-rv64 tty1
sid-rv64 login: root"

Interesting!
Since the card does not have keyboard , I cannot type on the 'HDMI screen'.

Is there any more introduction to login from 'HDMI screen' and start the GUI ?
Thanks

Is L1 data caches are inclusive in the L2 cache ?

//TODO L1 status tracking into L2 need to be exact, so need to notify when going from shared to invalid/another line.
https://github.com/SpinalHDL/NaxRiscv/blob/main/src/main/scala/naxriscv/lsu/DataCache.scala#L695

i am wondering if it is in to do list ?

is cache in multicore non coherent ?

https://github.com/SpinalHDL/NaxRiscv/blob/main/src/main/scala/naxriscv/platform/litex/NaxSoc.scala#L89

nonCoherent = cache.down

what does it mean ?

Dear Charles,

How do I add an L2 Data cache refill counter within withL2 block ?

    val scope = new ScopeFiber()
    scope.up at 0x04000000 of peripheral.bus
    if(withL2) {
      scope.add(l2.cache.logic.cache.events.acquire.hit, 0xF00)  //acquire is used by data cache
      scope.add(l2.cache.logic.cache.events.acquire.miss, 0xF04)
      scope.add(l2.cache.logic.cache.events.getPut.hit, 0xF20)   //getPut is used by instruction cache refill and DMA
      scope.add(l2.cache.logic.cache.events.getPut.miss, 0xF24)
    }

I guess this is for L1 cache

   for((nax, i) <- naxes.zipWithIndex) nax.plugins.foreach {
     case p: FetchCachePlugin => scope.add(p.logic.refill.fire, i*0x80 + 0x000)
     case p: DataCachePlugin => {
       scope.add(p.logic.cache.refill.push.fire, i * 0x80 + 0x010)
       scope.add(p.logic.cache.writeback.push.fire, i * 0x80 + 0x014)
     }
     case _ =>
   }
 }
 

In addition to the L2 cache miss counter, is SCOPE_HART_DCACHE_REFILL for L1 Dcache inside ext/NaxSoftware/baremetal/socdemo ?

#define SCOPE_HART_DCACHE_REFILL 0x10

    //read SCOPE_HART0_DCACHE_REFILL
    la x1, SCOPE_HART0 + SCOPE_HART_DCACHE_REFILL
    lw x10, 0(x1)

Thank you so much :)

Hello!
I'm trying to create a custom configuration where DDR memory starts at address 0 and other regions are at 0x40000000+.

But as soon as I remove "p" type region from address 0 I get an exception. Could you please help me figure out what is wrong?

$ sbt "runMain naxriscv.platform.litex.NaxGen \
--netlist-name=NaxRiscvLitex_5x --netlist-directory=. \
--reset-vector=0 --xlen=32 --cpu-count=1 --l2-bytes=131072 \
--l2-ways=8 --litedram-width=128 \
--memory-region=1073741824,3221225472,io,p \
--memory-region=0,1073741824,rwxc,m \
--memory-region=1073741824,1073741824,rw,p \
--memory-region=4026531840,65536,rw,p \
--scala-file=/Users/vadzim/Downloads/ecp5/litex/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/configs/gen.scala"

[info] welcome to sbt 1.6.0 (Azul Systems, Inc. Java 17.0.7)
[info] loading settings for project naxriscv-build from plugins.sbt ...
[info] loading project definition from /Users/vadzim/Downloads/ecp5/litex/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/ext/NaxRiscv/project
[info] loading settings for project root from build.sbt ...
[info] loading settings for project spinalhdl-build from plugin.sbt ...
[info] loading project definition from /Users/vadzim/Downloads/ecp5/litex/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/ext/NaxRiscv/ext/SpinalHDL/project
[info] loading settings for project all from build.sbt ...
[info] set current project to NaxRiscv (in build file:/Users/vadzim/Downloads/ecp5/litex/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/ext/NaxRiscv/)
[info] running (fork) naxriscv.platform.litex.NaxGen --netlist-name=NaxRiscvLitex_5x --netlist-directory=. --reset-vector=0 --xlen=32 --cpu-count=1 --l2-bytes=131072 --l2-ways=8 --litedram-width=128 --memory-region=1073741824,3221225472,io,p --memory-region=0,1073741824,rwxc,m --memory-region=1073741824,1073741824,rw,p --memory-region=4026531840,65536,rw,p --scala-file=/Users/vadzim/Downloads/ecp5/litex/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/configs/gen.scala
[info] [Runtime] SpinalHDL dev    git head : 9c82ff197e1ca17e98af75a77b470a0fda61fcfd
[info] [Runtime] JVM max memory : 4096.0MiB
[info] [Runtime] Current date : 2023.10.28 22:22:56
[info] [Progress] at 0.000 : Elaborate components
[info] memoryRegions: Seq[naxriscv.platform.litex.LitexMemoryRegion] = ArrayBuffer(LitexMemoryRegion(SM(0x40000000, 0xc0000000),io,p), LitexMemoryRegion(SM(0x0, 0x40000000),rwxc,m), LitexMemoryRegion(SM(0x40000000, 0x40000000),rw,p), LitexMemoryRegion(SM(0xf0000000, 0x10000),rw,p))
[info] LitexMemoryRegion(SM(0x40000000, 0xc0000000),io,p)
[info] LitexMemoryRegion(SM(0x0, 0x40000000),rwxc,m)
[info] LitexMemoryRegion(SM(0x40000000, 0x40000000),rw,p)
[info] LitexMemoryRegion(SM(0xf0000000, 0x10000),rw,p)
[info] import scala.collection.mutable.ArrayBuffer
[info] import naxriscv.utilities.Plugin
[info] import naxriscv.platform.litex.LitexMemoryRegion
[info] import spinal.lib.bus.misc.SizeMapping
[info] plugins: scala.collection.mutable.ArrayBuffer[naxriscv.utilities.Plugin] = ArrayBuffer(DocPlugin, MmuPlugin, FetchPlugin, PcPlugin, FetchCachePlugin, AlignerPlugin, FrontendPlugin, DecompressorPlugin, DecoderPlugin, integer_RfTranslationPlugin, RfDependencyPlugin, integer_RfAllocationPlugin, DispatchPlugin, BranchContextPlugin, HistoryPlugin, DecoderPredictionPlugin, BtbPlugin, GSharePlugin, Lsu2Plugin, DataCachePlugin, RobPlugin, CommitPlugin, integer_RegFilePlugin, CommitDebugFilterPlugin, CsrRamPlugin, PrivilegedPlugin, PerformanceCounterPlugin, ALU0_ExecutionUnitBase, ALU0_IntFormatPlugin, ALU0_SrcPlugin, ALU0_IntAluPlug...
[info] **********************************************************************************************
[info] [Warning] Elaboration failed (0 error).
[info]           Spinal will restart with scala trace to help you to find the problem.
[info] **********************************************************************************************
[info] [Progress] at 2.709 : Elaborate components
[info] memoryRegions: Seq[naxriscv.platform.litex.LitexMemoryRegion] = ArrayBuffer(LitexMemoryRegion(SM(0x40000000, 0xc0000000),io,p), LitexMemoryRegion(SM(0x0, 0x40000000),rwxc,m), LitexMemoryRegion(SM(0x40000000, 0x40000000),rw,p), LitexMemoryRegion(SM(0xf0000000, 0x10000),rw,p))
[info] LitexMemoryRegion(SM(0x40000000, 0xc0000000),io,p)
[info] LitexMemoryRegion(SM(0x0, 0x40000000),rwxc,m)
[info] LitexMemoryRegion(SM(0x40000000, 0x40000000),rw,p)
[info] LitexMemoryRegion(SM(0xf0000000, 0x10000),rw,p)
[info] import scala.collection.mutable.ArrayBuffer
[info] import naxriscv.utilities.Plugin
[info] import naxriscv.platform.litex.LitexMemoryRegion
[info] import spinal.lib.bus.misc.SizeMapping
[info] plugins: scala.collection.mutable.ArrayBuffer[naxriscv.utilities.Plugin] = ArrayBuffer(DocPlugin, MmuPlugin, FetchPlugin, PcPlugin, FetchCachePlugin, AlignerPlugin, FrontendPlugin, DecompressorPlugin, DecoderPlugin, integer_RfTranslationPlugin, RfDependencyPlugin, integer_RfAllocationPlugin, DispatchPlugin, BranchContextPlugin, HistoryPlugin, DecoderPredictionPlugin, BtbPlugin, GSharePlugin, Lsu2Plugin, DataCachePlugin, RobPlugin, CommitPlugin, integer_RegFilePlugin, CommitDebugFilterPlugin, CsrRamPlugin, PrivilegedPlugin, PerformanceCounterPlugin, ALU0_ExecutionUnitBase, ALU0_IntFormatPlugin, ALU0_SrcPlugin, ALU0_IntAluPlug...
[error] Exception in thread "main" scala.MatchError: spinal.lib.bus.misc.NeverMapping$@4340533c (of class spinal.lib.bus.misc.NeverMapping$)
[error] 	at spinal.lib.bus.misc.SizeMapping.spinal$lib$bus$misc$SizeMapping$$rec$1(Misc.scala:300)
[error] 	at spinal.lib.bus.misc.SizeMapping.intersectImpl(Misc.scala:315)
[error] 	at spinal.lib.bus.misc.AddressMapping$class.intersect(Misc.scala:111)
[error] 	at spinal.lib.bus.misc.SizeMapping.intersect(Misc.scala:236)
[error] 	at spinal.lib.system.tag.MemoryConnection$$anonfun$getMemoryTransfers$2$$anonfun$2.apply(Bus.scala:105)
[error] 	at spinal.lib.system.tag.MemoryConnection$$anonfun$getMemoryTransfers$2$$anonfun$2.apply(Bus.scala:102)
[error] 	at scala.collection.TraversableLike$$anonfun$map$1.apply(TraversableLike.scala:234)
[error] 	at scala.collection.TraversableLike$$anonfun$map$1.apply(TraversableLike.scala:234)
[error] 	at scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59)
[error] 	at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48)
[error] 	at scala.collection.TraversableLike$class.map(TraversableLike.scala:234)
[error] 	at scala.collection.AbstractTraversable.map(Traversable.scala:104)
[error] 	at spinal.lib.system.tag.MemoryConnection$$anonfun$getMemoryTransfers$2.apply(Bus.scala:102)
[error] 	at spinal.lib.system.tag.MemoryConnection$$anonfun$getMemoryTransfers$2.apply(Bus.scala:100)
[error] 	at spinal.lib.system.tag.MappedNode$$anonfun$foreachSlave$1.apply(Bus.scala:69)
[error] 	at spinal.lib.system.tag.MappedNode$$anonfun$foreachSlave$1.apply(Bus.scala:66)
[error] 	at scala.collection.mutable.LinkedHashSet.foreach(LinkedHashSet.scala:93)
[error] 	at spinal.core.SpinalTagReady$class.foreachTag(Trait.scala:696)
[error] 	at spinal.lib.bus.fabric.Node.foreachTag(Node.scala:6)
[error] 	at spinal.lib.system.tag.MappedNode.foreachSlave(Bus.scala:66)
[error] 	at spinal.lib.system.tag.MemoryConnection$.getMemoryTransfers(Bus.scala:100)
[error] 	at spinal.lib.system.tag.MemoryConnection$.getMemoryTransfers(Bus.scala:84)
[error] 	at spinal.lib.bus.tilelink.fabric.TransferFilter$$anonfun$1$$anon$1.<init>(TransferFilter.scala:64)
[error] 	at spinal.lib.bus.tilelink.fabric.TransferFilter$$anonfun$1.apply(TransferFilter.scala:42)
[error] 	at spinal.lib.bus.tilelink.fabric.TransferFilter$$anonfun$1.apply(TransferFilter.scala:42)
[error] 	at spinal.core.fiber.Fiber$$anonfun$1.apply(Fiber.scala:32)
[error] 	at spinal.core.fiber.package$$anonfun$1.apply$mcV$sp(package.scala:16)
[error] 	at spinal.core.fiber.AsyncThread$$anonfun$1.apply$mcV$sp(AsyncThread.scala:59)
[error] 	at spinal.core.fiber.EngineContext$$anonfun$newJvmThread$1.apply$mcV$sp(AsyncCtrl.scala:39)
[error] 	at spinal.sim.JvmThread.run(SimManager.scala:51)
[error] Nonzero exit code returned from runner: 1
[error] (Compile / runMain) Nonzero exit code returned from runner: 1
[error] Total time: 7 s, completed Oct 28, 2023, 10:22:59 PM

Hi,

I the the plugin for PeripheralAXILite4

plugins += new LsuPeripheralAxiLite4(ioDataWidth = xlen)

Is there any plugins for AXI4? Also, where can I find a list of plugins for naxrisc?

Thank you so much,
Duc

Hi,

I wonder whether it will be possible to compile and produce one Verilog code by compiling all branches or branches (like switch checkout coherency & SBT ) we want to see to Verilog code.

sbt "runMain naxriscv.Gen"

For example, there are extra scala files & and the same files have an extra line of code in the coherency branch; if we switch to the coherency branch and compile it with sbt "runMain naxriscv.Gen" , it throws some errors. Is there any solution to this problem?

I also copied those extra Scala codes in the main branch from the coherency branch and tried to compile it, but it did not work. I can not see iRefill , iWait , dRefill , dWriteback in compiled verilog code.

hsubedi@kronos:~/instruction_test_bed/nax_riscv/NaxRiscv$ l
assets/ build.sbt ext/ LICENSE logs/ nax.h NaxRiscvSynt.v NaxRiscv.v output/ project/ README.md src/ target/

hsubedi@kronos:~/instruction_test_bed/nax_riscv/NaxRiscv$ git branch -a
coherency

• main
  remotes/origin/HEAD -> origin/main
  remotes/origin/coherency
  remotes/origin/dev
  remotes/origin/fast-reschedule
  remotes/origin/fix_fetch_cache_plugin_mem_rsp_ready
  remotes/origin/fpu
  remotes/origin/jtag
  remotes/origin/lsu2
  remotes/origin/lsu_peripheral_store_cmd_ahead
  remotes/origin/main
  remotes/origin/reuse_licenses
  remotes/origin/riscv-debug
  hsubedi@kronos:~/instruction_t

Hi,

I wanted to ask if the 64-bit NaxRiscv can run Linux. I followed the steps to run Linux with naxriscv rv32ima and it works well, but ran into issues (failures) when I switched to a 64-bit core.
Could you please give me some pointers to run Linux using 64-bit core? Thanks!

Many times, we need to integrate systemverilog/verilog (or languages ​​that can generate them) into our SpinalHDL programs. In this process we need to define some compressed Bundles, such as:

case class AxiLite4DirectDemo(AW:Int, DW:Int, num:Int) extends Bundle with IMasterSlave {
    val STRBW = DW / 8
    val aw_addr = UInt(AW * num bits)
    val aw_valid = UInt(num bits)
    val aw_ready = UInt(num bits)
    val w_data = UInt(DW * num bits)
    val w_strb = UInt(STRBW * num bits)
    val w_valid = UInt(num bits)
    val w_ready = UInt(num bits)
    val b_resp = UInt(2 * num bits)
    val b_valid = UInt(num bits)
    val b_ready = UInt(num bits)
    val ar_addr = UInt(AW * num bits)
    val ar_valid = UInt(num bits)
    val ar_ready = UInt(num bits)
    val r_data = UInt(DW * num bits)
    val r_resp = UInt(2 * num bits)
    val r_valid = UInt(num bits)
    val r_ready = UInt(num bits)
    override def asMaster(): Unit = {
      in(b_resp, b_valid, aw_ready, w_ready, ar_ready, r_data, r_resp, r_valid)
      out(aw_addr, aw_valid, w_data, w_strb, w_valid, b_ready, ar_addr, ar_valid, r_ready)
    }
  }

For the convenience of use, we usually define it like this when using:

 Vec((AxiLite4Demo(AW, DW, 1)), num)

So, we need a helper that maps from (AxiLite4Demo(AW, DW, num)) to Vec((AxiLite4Demo(AW, DW, 1)), num). Of course, the more general the better. I have implemented a very low program to do this. There may be some situations that I have not considered, and the generality is not good. So, is there a better implementation?
My code is as follows:

object UnpackedBundlePlay extends App{
  case class AxiLite4Demo(AW:Int, DW:Int, num:Int) extends Bundle with IMasterSlave {
    val STRBW = DW / 8
    val aw_addr = UInt(AW * num bits)
    val aw_valid = UInt(num bits)
    val aw_ready = UInt(num bits)
    val w_data = UInt(DW * num bits)
    val w_strb = UInt(STRBW * num bits)
    val w_valid = UInt(num bits)
    val w_ready = UInt(num bits)
    val b_resp = UInt(2 * num bits)
    val b_valid = UInt(num bits)
    val b_ready = UInt(num bits)
    val ar_addr = UInt(AW * num bits)
    val ar_valid = UInt(num bits)
    val ar_ready = UInt(num bits)
    val r_data = UInt(DW * num bits)
    val r_resp = UInt(2 * num bits)
    val r_valid = UInt(num bits)
    val r_ready = UInt(num bits)
    def unpacked(): Vec[AxiLite4Demo] = new Composite(this, "unpacked") {
      val ret = Vec((AxiLite4Demo(AW, DW, 1)), num)
      val direct = self.elements.map { g => g._2.getDirection }
      (ret.map(_.elements).transpose zip self.elements).zip(direct).map { case ((r, s), d) =>
        if(d == `in`) (r.map(_._2) zip s._2.asBits.subdivideIn(r.head._2.getBitsWidth bits)).map{case(i,j) => i. assignFromBits(j)}
        else s._2.assignFromBits(Cat(r.map(_._2)))
      }
    }.ret
    def packed(va: Vec[AxiLite4Demo]):Unit = new AreaObject {
      va <> unpacked()
    }
    override def asMaster(): Unit = {
      in(b_resp, b_valid, aw_ready, w_ready, ar_ready, r_data, r_resp, r_valid)
      out(aw_addr, aw_valid, w_data, w_strb, w_valid, b_ready, ar_addr, ar_valid, r_ready)
    }
  }
  SpinalConfig().generateSystemVerilog(new Module{
    val io = new Bundle{
      val ain = slave( AxiLite4Demo(8,32,4))
      val aout= Vec(master(AxiLite4Demo(8,32,1)), 4)
    }
    io.aout <> io.ain.unpacked()
  }.setDefinitionName("UnpackedMod"))
  SpinalConfig().generateSystemVerilog(new Module{
    val io = new Bundle{
      val aout = master(AxiLite4Demo(8,32,4))
      val ain = Vec(slave(AxiLite4Demo(8,32,1)), 4)
    }
    io.aout.packed(io.ain)
  }.setDefinitionName("PackedMod"))
}

By the way, the user-defined instruction flow has been run through, and the parameter system is also good to use. It is roughly used as follows:

object TestModPlugin extends AreaObject{
  val P = NaxParameter[TestModPlugin_P]
}
...var p:TestModPlugin_P...
  create config {
    TestModPlugin.P.set(p)
  }

Thank you very much!

I am wondering of on chip debugger for NaxRISC V to monitor the change in register value like of CSR and any other variable.

If i have to run in Verilator terminal as of II. b) Debug Briey SoC with Verilator +OpenOCD + GDB
https://thuchoang90.github.io/project/2020/07/23/VexRiscv.html

like src/openocd -f tcl/interface/jtag_tcp.cfg -c "set NAX_CPU0_YAML /home/hsubedi/RISC_V_PROJECT/NaxRiscv/cpu0.yaml" -f tcl/target/Nax.cfg

I am wondering Why there is no Nax.cfg in https://github.com/SpinalHDL/openocd_riscv/tree/riscv_spinal/tcl/target

but for demo there is briey.cfg

Hi @Dolu1990,

I'm currently studying the Lsu2 plugin, and I may have an optimisation to suggest.

When a load instruction is processed in sharedPip, we check whether an older store instruction points to the same address in the checkSqMask and checkSqArbi stages.
If we detect an older store instruction with the same address, we have OLDER_STORE_HIT = True, and if this store is not waiting for address translation, we have OLDER_STORE_BYPASS_SUCCESS = True.

So, if this is the case, we're performing store-to-load forwarding, the data from the store is transmitted to the load, and written to the register.

Finally, if I've understood correctly, at the ctrl stage, we should enter the SUCCESS state, to indicate that the load instruction has been executed successfully. This is the case when the cache response is a cache hit.

However when the cache response in cacheRsp stage is a cache miss, we enter LOAD_MISS state in ctrl stage as rsp.redo = True.

We will have to wait for the cache refill before entering the SUCCESS state, even if we already have the data we need to load.

My suggestion is to modify the above line in the Lsu2 plugin to avoid the LOAD_MISS state and enter the SUCCESS state directly when there is a store-to-load forwarding.

}.elsewhen(IS_LOAD && rsp.redo && !OLDER_STORE_BYPASS_SUCCESS) {

By doing this :

• the cache will still be refilled, which is a good thing if subsequent load instructions point to that cache line.
• the store-to-load forwarding is optimised and saves clock cycles.

I hope I've understood your plugin correctly, and that I haven't forgotten something that would make my suggestion invalid.

Thank you in advance for your feedback

It is an interesting project and I am going to study it,the goal is to be able add FPU. I find the src/test/scala/naxriscv/NaxRiscvRegression.scala, Do you use it to run regression test ? How to run it ?

On running make compile, i get the following errors. Kindly help.

Hi, when I use idea build NaxRiscv which is a wonderful project for learning cpu design, it's build.sbt need spinalHDL 1.6.5, however this repo(SpinalHDLTemplate) version isn't it and I found content of SpinalHDL has updated. Can you help me solve it by update spinalHDLTemplate's build.sbt version. Thanks!

Log
[info] welcome to sbt 1.6.0 (Ubuntu Java 11.0.20)
[info] loading settings for project naxriscv-build from plugins.sbt ...
[info] loading project definition from /home/jingpo/Downloads/NaxRiscv/project
[info] loading settings for project root from build.sbt ...
[info] loading settings for project spinalhdl-build from plugin.sbt ...
[info] loading project definition from /home/jingpo/Downloads/SpinalHDL/project
[info] loading settings for project all from build.sbt ...
[info] set current project to NaxRiscv (in build file:/home/jingpo/Downloads/NaxRiscv/)
[info] compiling 108 Scala sources to /home/jingpo/Downloads/NaxRiscv/target/scala-2.11/classes ...
[error] error while loading , Error accessing /home/jingpo/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.11/3.2.5/scalactic_2.11-3.2.5.jar
[error] ## Exception when compiling 108 sources to /home/jingpo/Downloads/NaxRiscv/target/scala-2.11/classes
[error] scala.reflect.internal.MissingRequirementError: object java.lang.Object in compiler mirror not found.
[error] scala.reflect.internal.MissingRequirementError$.signal(MissingRequirementError.scala:17)
[error] scala.reflect.internal.MissingRequirementError$.notFound(MissingRequirementError.scala:18)
[error] scala.reflect.internal.Mirrors$RootsBase.getModuleOrClass(Mirrors.scala:53)
[error] scala.reflect.internal.Mirrors$RootsBase.getModuleOrClass(Mirrors.scala:45)
[error] scala.reflect.internal.Mirrors$RootsBase.getModuleOrClass(Mirrors.scala:45)
[error] scala.reflect.internal.Mirrors$RootsBase.getModuleOrClass(Mirrors.scala:66)
[error] scala.reflect.internal.Mirrors$RootsBase.getClassByName(Mirrors.scala:102)
[error] scala.reflect.internal.Mirrors$RootsBase.getRequiredClass(Mirrors.scala:105)
[error] scala.reflect.internal.Definitions$DefinitionsClass.ObjectClass$lzycompute(Definitions.scala:257)
[error] scala.reflect.internal.Definitions$DefinitionsClass.ObjectClass(Definitions.scala:257)
[error] scala.reflect.internal.Definitions$DefinitionsClass.init(Definitions.scala:1390)
[error] scala.tools.nsc.Global$Run.(Global.scala:1242)
[error] xsbt.ZincCompiler$ZincRun.(CallbackGlobal.scala:80)
[error] xsbt.CachedCompiler0.run(CompilerBridge.scala:161)
[error] xsbt.CachedCompiler0.run(CompilerBridge.scala:134)
[error] xsbt.CompilerBridge.run(CompilerBridge.scala:39)
[error] sbt.internal.inc.AnalyzingCompiler.compile(AnalyzingCompiler.scala:91)
[error] sbt.internal.inc.MixedAnalyzingCompiler.$anonfun$compile$7(MixedAnalyzingCompiler.scala:192)
[error] scala.runtime.java8.JFunction0$mcV$sp.apply(JFunction0$mcV$sp.java:23)
[error] sbt.internal.inc.MixedAnalyzingCompiler.timed(MixedAnalyzingCompiler.scala:247)
[error] sbt.internal.inc.MixedAnalyzingCompiler.$anonfun$compile$4(MixedAnalyzingCompiler.scala:182)
[error] sbt.internal.inc.MixedAnalyzingCompiler.$anonfun$compile$4$adapted(MixedAnalyzingCompiler.scala:163)
[error] sbt.internal.inc.JarUtils$.withPreviousJar(JarUtils.scala:239)
[error] sbt.internal.inc.MixedAnalyzingCompiler.compileScala$1(MixedAnalyzingCompiler.scala:163)
[error] sbt.internal.inc.MixedAnalyzingCompiler.compile(MixedAnalyzingCompiler.scala:210)
[error] sbt.internal.inc.IncrementalCompilerImpl.$anonfun$compileInternal$1(IncrementalCompilerImpl.scala:528)
[error] sbt.internal.inc.IncrementalCompilerImpl.$anonfun$compileInternal$1$adapted(IncrementalCompilerImpl.scala:528)
[error] sbt.internal.inc.Incremental$.$anonfun$apply$5(Incremental.scala:177)
[error] sbt.internal.inc.Incremental$.$anonfun$apply$5$adapted(Incremental.scala:175)
[error] sbt.internal.inc.Incremental$$anon$2.run(Incremental.scala:461)
[error] sbt.internal.inc.IncrementalCommon$CycleState.next(IncrementalCommon.scala:116)
[error] sbt.internal.inc.IncrementalCommon$$anon$1.next(IncrementalCommon.scala:56)
[error] sbt.internal.inc.IncrementalCommon$$anon$1.next(IncrementalCommon.scala:52)
[error] sbt.internal.inc.IncrementalCommon.cycle(IncrementalCommon.scala:263)
[error] sbt.internal.inc.Incremental$.$anonfun$incrementalCompile$8(Incremental.scala:416)
[error] sbt.internal.inc.Incremental$.withClassfileManager(Incremental.scala:503)
[error] sbt.internal.inc.Incremental$.incrementalCompile(Incremental.scala:403)
[error] sbt.internal.inc.Incremental$.apply(Incremental.scala:169)
[error] sbt.internal.inc.IncrementalCompilerImpl.compileInternal(IncrementalCompilerImpl.scala:528)
[error] sbt.internal.inc.IncrementalCompilerImpl.$anonfun$compileIncrementally$1(IncrementalCompilerImpl.scala:482)
[error] sbt.internal.inc.IncrementalCompilerImpl.handleCompilationError(IncrementalCompilerImpl.scala:332)
[error] sbt.internal.inc.IncrementalCompilerImpl.compileIncrementally(IncrementalCompilerImpl.scala:420)
[error] sbt.internal.inc.IncrementalCompilerImpl.compile(IncrementalCompilerImpl.scala:137)
[error] sbt.Defaults$.compileIncrementalTaskImpl(Defaults.scala:2366)
[error] sbt.Defaults$.$anonfun$compileIncrementalTask$2(Defaults.scala:2316)
[error] sbt.internal.server.BspCompileTask$.$anonfun$compute$1(BspCompileTask.scala:30)
[error] sbt.internal.io.Retry$.apply(Retry.scala:46)
[error] sbt.internal.io.Retry$.apply(Retry.scala:28)
[error] sbt.internal.io.Retry$.apply(Retry.scala:23)
[error] sbt.internal.server.BspCompileTask$.compute(BspCompileTask.scala:30)
[error] sbt.Defaults$.$anonfun$compileIncrementalTask$1(Defaults.scala:2314)
[error] scala.Function1.$anonfun$compose$1(Function1.scala:49)
[error] sbt.internal.util.$tilde$greater.$anonfun$$u2219$1(TypeFunctions.scala:62)
[error] sbt.std.Transform$$anon$4.work(Transform.scala:68)
[error] sbt.Execute.$anonfun$submit$2(Execute.scala:282)
[error] sbt.internal.util.ErrorHandling$.wideConvert(ErrorHandling.scala:23)
[error] sbt.Execute.work(Execute.scala:291)
[error] sbt.Execute.$anonfun$submit$1(Execute.scala:282)
[error] sbt.ConcurrentRestrictions$$anon$4.$anonfun$submitValid$1(ConcurrentRestrictions.scala:265)
[error] sbt.CompletionService$$anon$2.call(CompletionService.scala:64)
[error] java.base/java.util.concurrent.FutureTask.run(FutureTask.java:264)
[error] java.base/java.util.concurrent.Executors$RunnableAdapter.call(Executors.java:515)
[error] java.base/java.util.concurrent.FutureTask.run(FutureTask.java:264)
[error] java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
[error] java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
[error] java.base/java.lang.Thread.run(Thread.java:829)
[error]
[error] scala.reflect.internal.MissingRequirementError: object java.lang.Object in compiler mirror not found.
[error] at scala.reflect.internal.MissingRequirementError$.signal(MissingRequirementError.scala:17)
[error] at scala.reflect.internal.MissingRequirementError$.notFound(MissingRequirementError.scala:18)
[error] at scala.reflect.internal.Mirrors$RootsBase.getModuleOrClass(Mirrors.scala:53)
[error] at scala.reflect.internal.Mirrors$RootsBase.getModuleOrClass(Mirrors.scala:45)
[error] at scala.reflect.internal.Mirrors$RootsBase.getModuleOrClass(Mirrors.scala:45)
[error] at scala.reflect.internal.Mirrors$RootsBase.getModuleOrClass(Mirrors.scala:66)
[error] at scala.reflect.internal.Mirrors$RootsBase.getClassByName(Mirrors.scala:102)
[error] at scala.reflect.internal.Mirrors$RootsBase.getRequiredClass(Mirrors.scala:105)
[error] at scala.reflect.internal.Definitions$DefinitionsClass.ObjectClass$lzycompute(Definitions.scala:257)
[error] at scala.reflect.internal.Definitions$DefinitionsClass.ObjectClass(Definitions.scala:257)
[error] at scala.reflect.internal.Definitions$DefinitionsClass.init(Definitions.scala:1390)
[error] at scala.tools.nsc.Global$Run.(Global.scala:1242)
[error] at xsbt.ZincCompiler$ZincRun.(CallbackGlobal.scala:80)
[error] at xsbt.CachedCompiler0.run(CompilerBridge.scala:161)
[error] at xsbt.CachedCompiler0.run(CompilerBridge.scala:134)
[error] at xsbt.CompilerBridge.run(CompilerBridge.scala:39)
[error] at sbt.internal.inc.AnalyzingCompiler.compile(AnalyzingCompiler.scala:91)
[error] at sbt.internal.inc.MixedAnalyzingCompiler.$anonfun$compile$7(MixedAnalyzingCompiler.scala:192)
[error] at scala.runtime.java8.JFunction0$mcV$sp.apply(JFunction0$mcV$sp.java:23)
[error] at sbt.internal.inc.MixedAnalyzingCompiler.timed(MixedAnalyzingCompiler.scala:247)
[error] at sbt.internal.inc.MixedAnalyzingCompiler.$anonfun$compile$4(MixedAnalyzingCompiler.scala:182)
[error] at sbt.internal.inc.MixedAnalyzingCompiler.$anonfun$compile$4$adapted(MixedAnalyzingCompiler.scala:163)
[error] at sbt.internal.inc.JarUtils$.withPreviousJar(JarUtils.scala:239)
[error] at sbt.internal.inc.MixedAnalyzingCompiler.compileScala$1(MixedAnalyzingCompiler.scala:163)
[error] at sbt.internal.inc.MixedAnalyzingCompiler.compile(MixedAnalyzingCompiler.scala:210)
[error] at sbt.internal.inc.IncrementalCompilerImpl.$anonfun$compileInternal$1(IncrementalCompilerImpl.scala:528)
[error] at sbt.internal.inc.IncrementalCompilerImpl.$anonfun$compileInternal$1$adapted(IncrementalCompilerImpl.scala:528)
[error] at sbt.internal.inc.Incremental$.$anonfun$apply$5(Incremental.scala:177)
[error] at sbt.internal.inc.Incremental$.$anonfun$apply$5$adapted(Incremental.scala:175)
[error] at sbt.internal.inc.Incremental$$anon$2.run(Incremental.scala:461)
[error] at sbt.internal.inc.IncrementalCommon$CycleState.next(IncrementalCommon.scala:116)
[error] at sbt.internal.inc.IncrementalCommon$$anon$1.next(IncrementalCommon.scala:56)
[error] at sbt.internal.inc.IncrementalCommon$$anon$1.next(IncrementalCommon.scala:52)
[error] at sbt.internal.inc.IncrementalCommon.cycle(IncrementalCommon.scala:263)
[error] at sbt.internal.inc.Incremental$.$anonfun$incrementalCompile$8(Incremental.scala:416)
[error] at sbt.internal.inc.Incremental$.withClassfileManager(Incremental.scala:503)
[error] at sbt.internal.inc.Incremental$.incrementalCompile(Incremental.scala:403)
[error] at sbt.internal.inc.Incremental$.apply(Incremental.scala:169)
[error] at sbt.internal.inc.IncrementalCompilerImpl.compileInternal(IncrementalCompilerImpl.scala:528)
[error] at sbt.internal.inc.IncrementalCompilerImpl.$anonfun$compileIncrementally$1(IncrementalCompilerImpl.scala:482)
[error] at sbt.internal.inc.IncrementalCompilerImpl.handleCompilationError(IncrementalCompilerImpl.scala:332)
[error] at sbt.internal.inc.IncrementalCompilerImpl.compileIncrementally(IncrementalCompilerImpl.scala:420)
[error] at sbt.internal.inc.IncrementalCompilerImpl.compile(IncrementalCompilerImpl.scala:137)
[error] at sbt.Defaults$.compileIncrementalTaskImpl(Defaults.scala:2366)
[error] at sbt.Defaults$.$anonfun$compileIncrementalTask$2(Defaults.scala:2316)
[error] at sbt.internal.server.BspCompileTask$.$anonfun$compute$1(BspCompileTask.scala:30)
[error] at sbt.internal.io.Retry$.apply(Retry.scala:46)
[error] at sbt.internal.io.Retry$.apply(Retry.scala:28)
[error] at sbt.internal.io.Retry$.apply(Retry.scala:23)
[error] at sbt.internal.server.BspCompileTask$.compute(BspCompileTask.scala:30)
[error] at sbt.Defaults$.$anonfun$compileIncrementalTask$1(Defaults.scala:2314)
[error] at scala.Function1.$anonfun$compose$1(Function1.scala:49)
[error] at sbt.internal.util.$tilde$greater.$anonfun$$u2219$1(TypeFunctions.scala:62)
[error] at sbt.std.Transform$$anon$4.work(Transform.scala:68)
[error] at sbt.Execute.$anonfun$submit$2(Execute.scala:282)
[error] at sbt.internal.util.ErrorHandling$.wideConvert(ErrorHandling.scala:23)
[error] at sbt.Execute.work(Execute.scala:291)
[error] at sbt.Execute.$anonfun$submit$1(Execute.scala:282)
[error] at sbt.ConcurrentRestrictions$$anon$4.$anonfun$submitValid$1(ConcurrentRestrictions.scala:265)
[error] at sbt.CompletionService$$anon$2.call(CompletionService.scala:64)
[error] at java.base/java.util.concurrent.FutureTask.run(FutureTask.java:264)
[error] at java.base/java.util.concurrent.Executors$RunnableAdapter.call(Executors.java:515)
[error] at java.base/java.util.concurrent.FutureTask.run(FutureTask.java:264)
[error] at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1128)
[error] at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:628)
[error] at java.base/java.lang.Thread.run(Thread.java:829)
[error] (Compile / compileIncremental) scala.reflect.internal.MissingRequirementError: object java.lang.Object in compiler mirror not found.
[error] Total time: 4 s, completed Aug 13, 2023, 2:00:20 PM

my java version is:

 openjdk 18.0.1.1 2022-04-22
 OpenJDK Runtime Environment (build 18.0.1.1+2-6)
 OpenJDK 64-Bit Server VM (build 18.0.1.1+2-6, mixed mode, sharing)

and I met an error

 dpr@myMacBook-Air NaxRiscv % sbt run
 copying runtime jar...
 java.lang.UnsupportedOperationException: The Security Manager is deprecated and will be removed in a future release
        at java.base/java.lang.System.setSecurityManager(System.java:416)
        at sbt.TrapExit$.installManager(TrapExit.scala:54)
        at sbt.StandardMain$.runManaged(Main.scala:187)
        at sbt.xMain$.$anonfun$run$8(Main.scala:102)
        at scala.util.DynamicVariable.withValue(DynamicVariable.scala:62)
        at scala.Console$.withIn(Console.scala:230)
        at sbt.internal.util.Terminal$.withIn(Terminal.scala:560)
        at sbt.internal.util.Terminal$.$anonfun$withStreams$1(Terminal.scala:350)
        at scala.util.DynamicVariable.withValue(DynamicVariable.scala:62)
        at scala.Console$.withOut(Console.scala:167)
        at sbt.internal.util.Terminal$.$anonfun$withOut$2(Terminal.scala:550)
        at scala.util.DynamicVariable.withValue(DynamicVariable.scala:62)
        at scala.Console$.withErr(Console.scala:196)
        at sbt.internal.util.Terminal$.withOut(Terminal.scala:550)
        at sbt.internal.util.Terminal$.withStreams(Terminal.scala:350)
        at sbt.xMain$.run(Main.scala:86)
        at java.base/jdk.internal.reflect.DirectMethodHandleAccessor.invoke(DirectMethodHandleAccessor.java:104)
        at java.base/java.lang.reflect.Method.invoke(Method.java:577)
        at sbt.internal.XMainConfiguration.run(XMainConfiguration.scala:83)
        at sbt.xMain.run(Main.scala:46)
        at xsbt.boot.Launch$.$anonfun$run$1(Launch.scala:149)
        at xsbt.boot.Launch$.withContextLoader(Launch.scala:176)
        at xsbt.boot.Launch$.run(Launch.scala:149)
        at xsbt.boot.Launch$.$anonfun$apply$1(Launch.scala:44)
        at xsbt.boot.Launch$.launch(Launch.scala:159)
        at xsbt.boot.Launch$.apply(Launch.scala:44)
        at xsbt.boot.Launch$.apply(Launch.scala:21)
        at xsbt.boot.Boot$.runImpl(Boot.scala:78)
        at xsbt.boot.Boot$.run(Boot.scala:73)
        at xsbt.boot.Boot$.main(Boot.scala:21)
        at xsbt.boot.Boot.main(Boot.scala)
[error] [launcher] error during sbt launcher: java.lang.UnsupportedOperationException: The Security Manager is deprecated and > will be removed in a future release

this error won't occur when using java 11, so is there a way to use java 18 in NaxRiscv?

Can I generate a simulation trace that includes the memory addresses of the instructions executed, along with the information if it was a cache hit or miss?

Hi,
Im trying to build a smp soc using NaxRiscv. I can find similar work as Litex done with VexRiscv. But I noticed that NaxRiscv's DCache is the one of write-back .
How to get the DCache read/write info from NaxRiscv ? and How to Invalidate /Modify DCache line externally(From SoC). It's too complex.
I think the simple start point is to change the write-back DCache with write-through one, and find a way so that invalidate the "dirty" line.
Thanks.

Hello!
I've found a strange situation when I simulate double same cores. They just...have different ability. They have same flash, same ram, same bus and same perp. But they just do like this:

So why can they be that? I just want to use your core to make a double core lockstep(I'll pull it when it tests completely), but this strange "characteristic" make it impossible.....
Wish for you help!

I came across this project today. I was wondering if you have any maximum frequency numbers for the Series-7 FPGAs? You state that one of your goals is to achieve higher single threaded throughput compared to your VexRiscv project, so I was wondering how much the increased complexity of the core drags down the maximum frequency.

It's ok to run runMain naxriscv.Gen

but when I type sbt "runMain naxriscv.platform.LitexGen", it failed

NaxRiscv ) sbt "runMain naxriscv.platform.LitexGen"
[info] welcome to sbt 1.6.0 (Private Build Java 1.8.0_342)
[info] loading settings for project naxriscv-build-build-build from metals.sbt ...
[info] loading project definition from /home/cb/final/NaxRiscv/project/project/project
[info] loading settings for project naxriscv-build-build from metals.sbt ...
[info] loading project definition from /home/cb/final/NaxRiscv/project/project
[success] Generated .bloop/naxriscv-build-build.json
[success] Total time: 0 s, completed Oct 29, 2022 9:50:36 PM
[info] loading settings for project naxriscv-build from metals.sbt,plugins.sbt ...
[info] loading project definition from /home/cb/final/NaxRiscv/project
[success] Generated .bloop/naxriscv-build.json
[success] Total time: 0 s, completed Oct 29, 2022 9:50:36 PM
[info] loading settings for project root from build.sbt ...
[info] loading settings for project spinalhdl-build from plugin.sbt ...
[info] loading project definition from /home/cb/final/SpinalHDL/project
[info] loading settings for project all from build.sbt ...
[info] set current project to NaxRiscv (in build file:/home/cb/final/NaxRiscv/)
[info] running (fork) naxriscv.platform.LitexGen 
[info] [Runtime] SpinalHDL dev    git head : c7871836c6ffd61afed7cdbefaa95218c610d5af
[info] [Runtime] JVM max memory : 1676.5MiB
[info] [Runtime] Current date : 2022.10.29 21:50:42
[info] [Progress] at 0.000 : Elaborate components
[info] memoryRegions: Seq[naxriscv.platform.LitexMemoryRegion] = ArrayBuffer()
[info] import scala.collection.mutable.ArrayBuffer
[info] import naxriscv.utilities.Plugin
[info] import naxriscv.platform.LitexMemoryRegion
[info] import spinal.lib.bus.misc.SizeMapping
[info] plugins: scala.collection.mutable.ArrayBuffer[naxriscv.utilities.Plugin] = ArrayBuffer()
[info] resetVector: Long = 0
[info] args: scala.collection.mutable.LinkedHashMap[String,Any] = Map()
[info] xlen: Int = 32
[info] jtagTap: Boolean = false
[info] jtagInstruction: Boolean = false
[info] debug: Boolean = false
[info] arg: [T](key: String, default: T)T
[info] res0: scala.collection.mutable.ArrayBuffer[naxriscv.utilities.Plugin] = ArrayBuffer()
[info] The main thread is stuck at :
[info]     sun.misc.Unsafe.park(Native Method)
[info]     java.util.concurrent.locks.LockSupport.park(LockSupport.java:175)
[info]     java.util.concurrent.locks.AbstractQueuedSynchronizer$ConditionObject.await(AbstractQueuedSynchronizer.java:2039)
[info]     java.util.concurrent.CyclicBarrier.dowait(CyclicBarrier.java:234)
[info]     java.util.concurrent.CyclicBarrier.await(CyclicBarrier.java:362)
[info]     spinal.sim.JvmThread.park(SimManager.scala:30)
[info]     naxriscv.platform.NaxRiscvLitex$$anon$1.<init>(Litex.scala:44)
[info]     naxriscv.platform.NaxRiscvLitex.<init>(Litex.scala:43)
[info]     naxriscv.platform.LitexGen$$anonfun$14.apply(Litex.scala:179)
[info]     naxriscv.platform.LitexGen$$anonfun$14.apply(Litex.scala:152)
[info]     spinal.sim.JvmThread.run(SimManager.scala:51)
[info] **********************************************************************************************
[info] [Warning] Elaboration failed (0 error).
[info]           Spinal will restart with scala trace to help you to find the problem.
[info] **********************************************************************************************
[info] [Progress] at 5.444 : Elaborate components
[info] memoryRegions: Seq[naxriscv.platform.LitexMemoryRegion] = ArrayBuffer()
[info] import scala.collection.mutable.ArrayBuffer
[info] import naxriscv.utilities.Plugin
[info] import naxriscv.platform.LitexMemoryRegion
[info] import spinal.lib.bus.misc.SizeMapping
[info] plugins: scala.collection.mutable.ArrayBuffer[naxriscv.utilities.Plugin] = ArrayBuffer()
[info] resetVector: Long = 0
[info] args: scala.collection.mutable.LinkedHashMap[String,Any] = Map()
[info] xlen: Int = 32
[info] jtagTap: Boolean = false
[info] jtagInstruction: Boolean = false
[info] debug: Boolean = false
[info] arg: [T](key: String, default: T)T
[info] res0: scala.collection.mutable.ArrayBuffer[naxriscv.utilities.Plugin] = ArrayBuffer()
[info] The main thread is stuck at :
[info]     sun.misc.Unsafe.park(Native Method)
[info]     java.util.concurrent.locks.LockSupport.park(LockSupport.java:175)
[info]     java.util.concurrent.locks.AbstractQueuedSynchronizer$ConditionObject.await(AbstractQueuedSynchronizer.java:2039)
[info]     java.util.concurrent.CyclicBarrier.dowait(CyclicBarrier.java:234)
[info]     java.util.concurrent.CyclicBarrier.await(CyclicBarrier.java:362)
[info]     spinal.sim.JvmThread.park(SimManager.scala:30)
[info]     naxriscv.platform.NaxRiscvLitex$$anon$1.<init>(Litex.scala:44)
[info]     naxriscv.platform.NaxRiscvLitex.<init>(Litex.scala:43)
[info]     naxriscv.platform.LitexGen$$anonfun$14.apply(Litex.scala:179)
[info]     naxriscv.platform.LitexGen$$anonfun$14.apply(Litex.scala:152)
[info]     spinal.sim.JvmThread.run(SimManager.scala:51)
[error] Exception in thread "main" java.lang.Exception: Can't find the service naxriscv.fetch.FetchCachePlugin
[error]         at naxriscv.utilities.Framework.getService(Framework.scala:106)
[error]         at naxriscv.utilities.Plugin$class.getService(Framework.scala:66)
[error]         at naxriscv.fetch.FetchAxi4.getService(FetchAxi4.scala:9)
[error]         at naxriscv.fetch.FetchAxi4$$anonfun$1$$anon$1.<init>(FetchAxi4.scala:14)
[error]         at naxriscv.fetch.FetchAxi4$$anonfun$1.apply(FetchAxi4.scala:13)
[error]         at naxriscv.fetch.FetchAxi4$$anonfun$1.apply(FetchAxi4.scala:13)
[error]         at naxriscv.utilities.Plugin$$anon$1$$anonfun$late$1$$anonfun$5.apply(Framework.scala:54)
[error]         at spinal.core.Area$class.rework(Area.scala:59)
[error]         at naxriscv.utilities.Framework.rework(Framework.scala:77)
[error]         at naxriscv.utilities.Plugin$$anon$1$$anonfun$late$1.apply(Framework.scala:52)
[error]         at spinal.core.fiber.package$$anonfun$1.apply$mcV$sp(package.scala:10)
[error]         at spinal.core.fiber.AsyncThread$$anonfun$1.apply$mcV$sp(AsyncThread.scala:59)
[error]         at spinal.core.fiber.EngineContext$$anonfun$newJvmThread$1.apply$mcV$sp(AsyncCtrl.scala:39)
[error]         at spinal.sim.JvmThread.run(SimManager.scala:51)
[error] Nonzero exit code returned from runner: 1
[error] (Compile / runMain) Nonzero exit code returned from runner: 1
[error] Total time: 10 s, completed Oct 29, 2022 9:50:48 PM

so what happened here? I'm sorry I do not understand the source code.

Hi,

Could you please let me know what maximum supported frequency of riscv in Xilinx device(like artix or virtex ultrascale, ultrascale plus)?

Thank you so much,
Duc

Hey!

I am using Linux on NaxRiscv, and I would like to monitor CPU performance using the hpmcountern registers. A quick test led me to believe that the associated bits of mcountinhibit are not cleared as reading hpmcounter3, hpmcounter4, hpmcounter5, and hpmcounter6 return 0.

I understand that I must modify the opensbi in order to change the content of mcountinhibit. Even after following the steps listed in linux-on-vexriscv, I do not manage to compile a opensbi firmware that successfully executes (i.e., it freezes at "liftoff!"). My guess is that the compiler I use is not the correct one. Could you indicate to me what compiler you are referring to with riscv-none-embed- or if I am missing something?

Also, do you think that mcountinhibit is the reason why the hpmcountern registers are always read as 0?

Thank you in advance for the help!

How to find executable code inside (/home/hsubedi/RISC_V_PROJECT/NaxRiscv) for each time we create new .elf file ( verilog ( with help of sbt "runMain naxriscv.Gen")--> with help of verilator ---> c++ (make -C src/test/cpp/naxriscv compile) ---->(then) executable ELF) ?

I am wondering if we update the spinalHDL code, How can we  read value of folllowing variable iRefill and iWait so we can read its value for cache re-fill or miss?

where can we find that .elf file which might have following variable:iRefill and iWait so it will be easy to debug ?

riscv32-unknown-elf-gdb .elf ( which .elf file should we load here )

to debug the following variables:iRefill and iWait and 'printf' to read the value of cache miss

val iRefill = add(0x840, i.logic.refill.fire)
val iWait = add(0x842, i.logic.refill.valid)

And this counter value?

def add(csrId : Int, probe : Bool) = new Area{
  val counter = Reg(UInt(32 bits)) init(0)
  when(probe.pull()){counter := counter + 1}
  csr.readWrite(counter, csrId)
} 

Dear Dolu1990, GPT4.0 has been released. Its coding ability is amazing. I hope we can actively embrace and promote it to reduce the usage threshold of spinalhdl or naxriscv. (PS: I have been doing AI algorithms for half a year now, but I don't want to give up on chip design because it is also my passion). Of course, there will be opportunities to seek cooperation with OpenAI in the future, and we can fine-tune our spinalhdl to a higher level of intelligence and natural language. The following is me, temporarily impromptu, chatting with new bing.

“你能帮我改写上面的代码吗，需求使用8比特数据的乘法或者16比特的乘法是通过naxriscv里的csr来配置的”

Sure! Here is the modified code that adds a custom instruction called SIMD_MUL that can perform multiplication of four 8-bit signed numbers and two 16-bit signed numbers. The requirement to use 8-bit or 16-bit data for multiplication is configured through a CSR in naxriscv:

class SimdAddPlugin extends Plugin[VexRiscv]{
  // Define a new instruction called SIMD_ADD
  object SIMD_ADD extends Stageable(new Bundle {
    val rs1 = Bits(32 bits)
    val rs2 = Bits(32 bits)
    val rd = Bits(32 bits)
  })

  // Define a new instruction called SIMD_MUL
  object SIMD_MUL extends Stageable(new Bundle {
    val rs1 = Bits(32 bits)
    val rs2 = Bits(32 bits)
    val rd = Bits(32 bits)
  })

  override def setup(pipeline: VexRiscv): Unit = {
    import pipeline._
    import pipeline.config._
    // Get the decoder service
    val decoderService = pipeline.service(classOf[DecoderService])

    // Add SIMD_ADD and SIMD_MUL as default instructions
    decoderService.addDefault(SIMD_ADD)
    decoderService.addDefault(SIMD_MUL)

    // Define the execute stage for SIMD_ADD
    val executeAdd = new Area {
      import executeAdd._
      // Get the inputs and output of SIMD_ADD
      val rs1 = executeAdd.input(SIMD_ADD.rs1)
      val rs2 = executeAdd.input(SIMD_ADD.rs2)
      val rd = executeAdd.output(SIMD_ADD.rd)

      // Add the two inputs and store the result in rd
      rd := rs1 + rs2
    }

    // Define the execute stage for SIMD_MUL
    val executeMul = new Area {
      import executeMul._
      // Get the inputs and output of SIMD_MUL
      val rs1 = executeMul.input(SIMD_MUL.rs1)
      val rs2 = executeMul.input(SIMD_MUL.rs2)
      val rd = executeMul.output(SIMD_MUL.rd)

      // Check if we should use 8-bit or 16-bit data for multiplication
      when(csrService.r(csrAddress)) {
        // Multiply four 8-bit signed numbers
        rd(7 downto 0) := (rs1(7 downto 0) * rs2(7 downto 0)) + (rs1(15 downto 8) * rs2(15 downto 8)) + (rs1(23 downto 16) * rs2(23 downto 16)) + (rs1(31 downto 24) * rs2(31 downto 24))
        rd(15 downto 8) := B"00000000"
      } otherwise {
        // Multiply two 16-bit signed numbers
        rd := (rs1.asSInt * rs2.asSInt).asBits.resized
      }
    }

    // Plug in the execute stage for SIMD_ADD to the pipeline
    executeAdd plug new Area {
      import executeAdd._
      // Specify that our plugin will never halt the pipeline, allowing the issue queue to statically wake up instructions which depend on its result.
      staticLatency=true
      // We specify here that our plugin will be executed when a SIMD_ADD instruction is detected
      onInstruction(SIMD_ADD){
        // We just add our execution logic to the execute stage for SIMD_ADD
        executeAdd
      }
    }

    // Plug in the execute stage for SIMD_MUL to the pipeline
    executeMul plug new Area {
      import executeMul._
      // Specify that our plugin will never halt the pipeline, allowing the issue queue to statically wake up instructions which depend on its result.
      staticLatency=true
      // We specify here that our plugin will be executed when a SIMD_MUL instruction is detected
      onInstruction(SIMD_MUL){
        // We just add our execution logic to the execute stage for SIMD_MUL
        executeMul
      }
    }
  }
}

I hope this helps! Let me know if you have any other questions.

I am having some trouble brining up a Nax core and the Rust riscv-rt library.

My code builds and loads into the softcore fine but traps quickly when accessing CSRs.

Source assembly is here: https://github.com/rust-embedded/riscv-rt/blob/master/asm.S
Here's the first few lines of my binary disassembly:

minisoc:        file format elf32-littleriscv
                                             
Disassembly of section .text:                
                                             
80000000 <_start>:                           
80000000: b7 00 00 80   lui     ra, 524288   
                                             
80000004 <.L0 >:                             
80000004: 67 80 80 00   jr      8(ra)        
                                             
80000008 <_abs_start>:                       
80000008: 73 50 40 30   csrwi   mie, 0       
                                             
8000000c <.L0 >:                             
8000000c: 73 50 40 34   csrwi   mip, 0       
                                             
80000010 <.L0 >:                             
80000010: 81 40         li      ra, 0        
                                             
80000012 <.L0 >:                             
80000012: 01 41         li      sp, 0        
                                             
80000014 <.L0 >:                             
80000014: 81 41         li      gp, 0

The core traps after 0x8000000C which jumps it back to 0x00000000.

Configuration is Config.plugins(withDebug = true, withEmbeddedJtagTap = true) with some peripherals.

I did try to hack in pieces of the interrupt controllers so maybe it's grabbing an erroneous external interrupt?

Any suggestions are appreciated!

Hi,

I used the generated code to synthesize in Vivado, but it doesnt work. This is the error.

Unexpected Assertion error in File r:/wall1/workspaces/wall724/sub/REL/2022.1/src/shared/synth/rtx/syn/gen/HARTGRamGenInfo.cxx Line 4583
An unrecoverable error has occurred, synthesis cancelled.
TclStackFree: incorrect freePtr. Call out of sequence?

Could you please let me know how to solve it?
Thank you.
Duc

The current usage is as follows:

  NaxScope.create(xlen = 32)
  val frame = new MyPlugins(plugins).framework

Can the parameter configuration and auto-negotiation mechanism be generalized and independent.
like this:
https://github.com/chipsalliance/cde/blob/master/cde/src/chipsalliance/rocketchip/config.scala

Thanks!

I ran the SocSim yesterday, an it works fine.
But,When I this :
sbt "runMain Gen64"

in src/test/cpp/naxriscv:
make compile -- It is OK

./obj_dir/VNaxRiscv --load-elf ../../../../ext/NaxSoftware/riscv-tests/rv32ui-p-addi --start-symbol test_2 --pass-symbol pass --fail-symbol fail --timeout 10000

Report :

Failure due to fail symbol encounter
TIME=430
LAST PC COMMIT=80000404
INCOMING SPIKE PC=80000408
ROB_ID=x2
FAILURE ???

https://docs.github.com/en/communities/setting-up-your-project-for-healthy-contributions/adding-a-license-to-a-repository

I am trying to ADD VPU to NaxRiscv.

Related to latest SpinalHDL update.
Two such errors in naxriscv.utilities.AllocatorMultiPort lines 63 and 92.
I have no clue how to solve them.

I found that a self-modifying code trigger the assertion *** INTEGER WRITE DATA DUT=40 REF=0 ***. Nax does not seem to support rewriting code sections, but spike seems to support rewriting code sections. Is this expected behavior?

This issue was found by a fuzzer (random generator) for hardware designs.

Reproduction steps:

1. Prepare the following assembly file in NaxSoftware's bare metal environment. The file path is /NaxRiscv/ext/NaxSoftware/baremetal/test/crt.S.

.globl _start
_start:
  la x6, target
  sb x0, 3(x6) // rewrite addi t2, t2, 64
  addi t1, t1, 64
target:
  addi t2, t2, 64
  nop
  nop
  nop
  nop
  ret

2. Compile with command make -C $NAXRISCV/ext/NaxSoftware/baremetal/test RISCV_PATH=$RISCV MARCH=rv32im MABI=ilp32.
3. Execute with command cd $NAXRISCV/src/test/cpp/naxriscv; ./obj_dir/VNaxRiscv --load-elf ../../../../ext/NaxSoftware/baremetal/test/build/test.elf --trace-ref --spike-debug.
4. The following output is generated.

*** INTEGER WRITE DATA DUT=40 REF=0 ***

TIME=264
LAST PC COMMIT=80000010
INCOMING SPIKE PC=ffffffff80000014
ROB_ID=x6
FAILURE ???

core   0: 0x80000000 (0x00000317) auipc   t1, 0x0
core   0: 3 0x80000000 (0x00000317) x 6 0x80000000
core   0: 0x80000004 (0x01030313) addi    t1, t1, 16
core   0: 3 0x80000004 (0x01030313) x 6 0x80000010
core   0: 0x80000008 (0x000301a3) sb      zero, 3(t1)
core   0: 3 0x80000008 (0x000301a3) mem 0x80000013 0x0
core   0: 0x8000000c (0x04030313) addi    t1, t1, 64
core   0: 3 0x8000000c (0x04030313) x 6 0x80000050
core   0: 0x80000010 (0x00038393) mv      t2, t2 <- addi t2, t2, 64 is dynamically rewritten
core   0: 3 0x80000010 (0x00038393) x 7 0x00000000

Hi ^^
I'm trying to run the debug module of NaxRiscv using GDB OpenOCD and Verilator, as mentioned in VexRiscv. But I don't have any ideas. Following the debug process of Vexriscv, I found that the problems were VNaxRiscv being unable to run, openod missing yaml files, and gdb missing uart files. How can I debug in Naxriscv? Could you give me some suggestions?

Hello!

I'm learning the code and the structure of Nax, and now I'm trying to build a soc with it. But I can't understand some settings of port paras.
As the issue says #28 ,fetchRange => Is used to specify on which memory address range the CPU is allowed to fetch instructions.But at this code
class FetchAxi4(ramDataWidth : Int, ioDataWidth : Int, toPeripheral : FetchL1Cmd => Bool ) extends Plugin
there's a para "toPeripheral ", this para seems doing the same thing(or just a opposite way)with the "fetchRange", it looks like they just take effect in the different place,Is there some misinterpretations?

And, is there any plans about building a multi-core system?Add something like Tilelink?(but the tilelink code of Rocket is....a little bit .....hard to understand?hhh)

Thank you for your help!

Hi !
When I excute riscv-tests with the config

    val l = Config.plugins(
      sideChannels = false, //WARNING, FOR TEST PURPOSES ONLY, turn to false for real stuff <3
      xlen = 64,
      withRdTime = false,
      aluCount = 2,
      decodeCount = 2,
      withRvc = true,
      withDebug = false,
      withEmbeddedJtagTap = false,
      debugTriggers = 0,
      withFloat = true,
      withDouble = true,
      lqSize = 16,
      sqSize = 16,
      resetVector = 0x80000000l
    )

I find the rv64si-p-wfi rv64mi-p-csr can't pass the test，can you tell me how to solve the problem? Thank You!

Hi,
https://github.com/google/CFU-Playground
They have added an acc. module and connected to VexRiscv.
Just as learned from NaxRiscv design earlier , it is not difficult to add custom instruction. But since of poor skill of SpanialHDL, it is hard for me to add an interface to send/receive instruction/result to external Acc.
Does any one have template or example to do this kind of work?
Thanks.

Hi !
I See a very complex statemachine in the PrivilegedPlugin,the code is between 720 and 966 lines，Can you show me a picture about how the statemachine works? Thank you very mush :)