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Name: Jose R Garcia
Type: User
Location: CT, USA
Jose R Garcia's Projects
cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
dapboot
Dapboot fork for GD32F150 devices includes nasty patch.
gd32usb2spi
Simple USB-to-SPI adapter firmware using the CDCACM driver. Designed to be used on the Sipeed Tang Premier FPGA board, to establish communication between the GD32F150 on-board processor and the Anlogic FPGA
goldschmidt_integer_divider_parallel
A Goldschmidt integer divider written in verilog. Similar to Newton-Raphson but the divison step can be pipelined.
iir_filter
IIR Parallel Filter
nanogpt_amd
The simplest, fastest repository for training/finetuning medium-sized GPTs. WIth minor changes for better support of AMD GPUs
open-source-fpga-bitcoin-miner
A completely open source implementation of a Bitcoin Miner for Anlogic EG4 FPGAs.
prjtang
Documenting the Anlogic FPGA bit-stream format.
rocm
AMD ROCm™ Software - GitHub Home
stx_cookbook
Altera Advanced Synthesis Cookbook 11.0
systemverilogsha256
SHA256 in (System-) Verilog / Open Source FPGA Miner
uvm-python-verification-lib
UVM Python Verification Agents Library
uvm_python_gen.vim
VIM / NeoVim plugin to auto-generate the shell for uvm-python verifiaction IP.
uvm_python_wishbone_pipeline_master
Wishbone Master(Pipelined) Bus Interface Verification Agent
uvm_python_wishbone_pipeline_slave
Wishbone Slave(Pipelined) Bus Interface Verification Agent
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