Comments (8)
Hi,
Yes that's "normal", as mip is a read only register in NaxRiscv :
We could easily turn it into allowing write.
csr.allowCsr(CSR.MIP)
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Is this something that should be "fixed"? That rust library seems to think the machine and supervisor CSRs should be writable, or at the least not an error.
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Is this something that should be "fixed"?
Yes ^^
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hardware fix required
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I patched in csr.allowCsr(CSR.MIP)
but that hasn't fixed the bug :/
I also tried adding a single bit to MIP as read/write but that didn't fix the trap either.
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I just tested in sim, and the core i have do not trap on mip writes (even without allowCsr)
Do you have a simulation wave ? Could i look at it ?
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AHHHHHH
You have compressed instruction set enabled in your assembly ( 81 40 li ra, 0 )
While the core do not implement it by default. you have to turn on withRvc = true ^^
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That was it! Thanks so much!
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Related Issues (20)
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- Problems about debug and Halt the Nax HOT 8
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- NaxRiscv sets sepc[0]=1 which is against the riscv privileged spec HOT 3
- How to customize hardware architecture HOT 15
- Does NaxRicv support S-mode? HOT 12
- Read data incorrectly when executing `c.lwsp` instruction HOT 9
- Wrong value of `sie` after trapping store_access_fault HOT 1
- [Bug Report] Executing `sfence.vma` under U-mode doesn't throw illegal inst exception
- Does NaxRiscv update mtval after trap illegal_inst? HOT 2
- Accessing addr 0x0000001e doesn't throw access fault exception HOT 3
- Question about the sizes of cache L2 & L1 HOT 2
- A trap is triggered when the pmpcfg register is read by csrr HOT 8
- storeFresh unused : trap-store_access_fault HOT 5
- WFI instruction HOT 11
- How to integrate my own IP HOT 3
- The check of the register Rd/Rs is not equal to zero is missing for some compressed instructions HOT 1
- Nax not trap on store fault
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