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This issue is an on going list of the device level LVS and CVC issues with caravel modules.
origin/develop commit 384a7d5
magic 8.3.133
The indentation of the list is intended to show the hierachy.
Unless otherwise indicated, CVC was run on the netlist extracted from GDS.

So Travis CI doesn't time out the build after 10 minutes.

Efabless hosted precheck runs 20 minutes, so adding a dummy (sleep; echo)& to fire at minute 7 and minute 14 should be more than sufficient. If it is straightforward to add a open_mpw_precheck flag that shows >0 but <100 lines of precheck output as they come in that would ofc be preferable.

• creation of useful IP such as DMA controller of high-speed capture IP not possible.

I think it should say "Caravel is a standard SoC harness" - not hardness!

Verification command for GL is not working inside the docker,
simulation is running in RTL mode only for BOTH -SIM=RTL and -SIM=GL command.

RTL command : make verify-wb_port -SIM=RTL
GL Command: make verify-wb_port -SIM=GL

For both case iverilog command executed is for RTL compile command without GL switch:

iverilog -DFUNCTIONAL -DSIM 

Look like SIM variable export function inside the docker is not working.

When I tried direct GL simulation, Test fails with internal core boot is working, but IO pad are going unknown.

Look like Caravel Gate Level Simulation setup is broken.

An example is this net in ring_osc2x13 which wasn’t explicitly declared, although there are many more. iverilog prints them all when attempting to build with the caravel module.

https://github.com/efabless/caravel/blob/4596e5f7a489ef9a31d71dd5ece7bdf3531ecbca/verilog/rtl/ring_osc2x13.v#L16

At the moment I’ve reverted the commit in my personal branch but am raising this issue as it’s up to the repo maintainers as to how/if the unconnected nets should be wired.

(I personally like using default_nettype none but was hesitant to include it my earlier wiring fix PR as I couldn't verify it at the time it by running the sim)

We see user_project_wrapper Port name mismatch between RTL & Gate level caravel.v

In RTL : caravel/verilog/rtl/caravel.v
user_project_wrapper mprj (
....
.la_oenb(la_oenb_user),

in Gate Level: caravel/verilog/gl/caravel.v
user_project_wrapper mprj (
......
.la_oen(

In user_project_wrapper has la_oenb port, where as gate level caravel.v has la_oen

• Add how to create a .v stub for my analog macro
• Add how to use Layout for signal traceability
• Add how to use SAK utils
• Information about the repo structure and how to contribute

Commit 694bfd3c5ee03d3716541b7b55bcd5fc13343bfd introduces interrupts in the user_project. However, this IO is not present in the instantiation of user_project

See the comment on: https://github.com/efabless/caravel/blob/master/verilog/rtl/user_project_wrapper.v#L68-L72

Needed for MPW-three: Put a glitch filter between the IRQ pin and the management core, using for example the glitch filter circuit used on the xres4v2 I/O pad, or else implement a simple digital glitch filter within the management SoC. This would allow the IRQ pin to be connected directly to a button.

However, there is hysteresis built into the GPIOv2 I/O pad, so the existing system (striVe or caravel MPW-one) should be tested to see if maybe it's not an issue in practice.

There doesn't seem to be any links in this repository to the awesome documentation at https://caravel-docs.readthedocs.io/en/moving-to-rst/index.html

There should be a quickstart telling how to get started with creating a user project. The document should be written in RST so it could be later incorporated into the Sphinx documentation.

In File : verilog/rtl/mgmt_core.v

caravel_clocking clocking(

Instance definition "clocking" is reserved System verilog variable,

If we enable the SV swiitch (-g2005-sv) is iverilog tool is reporting this error.

For the next spin enabling the PCPI would be handy for extending the RV32 instruction set. I'm not sure if this is possible given the number of pins required.

Expected behaviour

We should have a script that would allow autogenerating the top-level diagram of Caravel chip based on the contents of verilog/rtl directory.

Tie unconnected inputs to constant zeros and explicitly list unconnected outputs for clarity.
https://github.com/efabless/caravel/blob/master/verilog/rtl/storage.v#L49

It seems the docs moved and it is currently it is empty?

Expected behaviour

The source code for the documentation should be available in the repository, along with the generation of the documentation in HTML and PDF formats.

Current behaviour

The documentation is currently available under doc/caravel_datasheet.pdf.

This issue covers initial work on creating readthedocs pipeline and rewriting the current documentation from doc/caravel_datasheet.pdf to the RST files for Sphinx documentation.

Hello, I am using my design as macro, and I want to insert it into the caravel project. I tried both caravel_user_project and caravel_user_project_analog. Both of them get stuck at certain step in the flow. So I am writing to see if I am doing something wrong. The upper figure is caravel_user_project_analog and lower one is caravel_user_project.

I'm attempting to harden my design using option 2 (https://github.com/efabless/caravel/tree/master/openlane#option-2). When I attempt make user_project_wrapper I get several errors and warnings and it finally errors out with:

[ERROR]: Floorplanning failed
[ERROR]: module decred_top not found in /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged.lef
[ERROR]: Check whether EXTRA_LEFS is set appropriately

I don't have any macros in my design so all of the code is listed under VERILOG_FILES, I don't have any blackbox files or LEF or GDS imports.

If I create a similar script as a separate design (like option 1), I can get through that type of flow. It seems that the script execution between the two options are different, at least in the beginning.

The script being used is https://github.com/SweeperAA/skywater130_decred_miner/blob/master/openlane/user_project_wrapper/config.tcl

I've also modified the interactive.tcl as the instructions indicated (https://github.com/SweeperAA/skywater130_decred_miner/blob/master/openlane/user_project_wrapper/interactive.tcl).

It is not known if unused inputs to the management area need to be terminated in the user space. To the best of my knowledge there's no documentation for how to treat these signals.

If they are not terminated then the digital gates will have undefined values and could lead to large increase in power. Will eFabless terminate these pins or is it the user's responsibility?

With 08cd6eb and 581068f the compiler directive ``default_nettype none` was introduced to some (not all) files, including all testbench files.
The directive requires that the type of nets of all ports in the modules must be defined.

The design of the management soc uses implicit port type declarations most of the time. Moreover the produced netlists from yosys do not include port type declarations!

Using any other simulator than Icarus Verilog, above described problem will result in "missing net type declarations" errors.

This problem is closely related to the google/skywater-pdk#198, where the use of implicit net type declarations was already discussed but without a resolution.

Due to the use of implicit declarations everywhere, I would suggest to remove the compiler directive ``default_nettype none`.

There must be reg_cf_do instead of reg_ena_do at line number 138 in simpleuart.

I am referring to the documentation page at Caravel Pinout Description [ https://caravel-harness.readthedocs.io/en/latest/pinout.html ]

The attached diagram shows the 4 signals in the pin description table

spi_sdo
spi_sck
spi_csb
spi_sdi

do not appear in the pinout table. Is this an error in the pinout table?

openlane: c077f963c23b53e2cd39656e3d21689537110707
caravel: 297a6cf (HEAD as of this issue)
skywater-pdk: 1ce480d61120895462adc03df617d39de7a0f76e (Master~4, pulled by openlane build)

[INFO]: Running Synthesis...

<snip>

5. Executing HIERARCHY pass (managing design hierarchy).

5.1. Analyzing design hierarchy..
ERROR: Module `\PASS' referenced in module `\DFFRAM' in cell `\MUX' is not part of the design.
[ERROR]: during executing: "yosys -c /openLANE_flow/scripts/synth_top.tcl -l /project/openlane/DFFRAM/runs/DFFRAM/logs/synthesis/yosys.log |& tee >&@stdout"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
child process exited abnormally

[ERROR]: Please check yosys  log file
[ERROR]: Dumping to /project/openlane/DFFRAM/runs/DFFRAM/error.log

    while executing
"try_catch [get_yosys_bin]  -c $::env(SYNTH_SCRIPT)  -l $::env(yosys_log_file_tag).log  |& tee $::env(TERMINAL_OUTPUT)"
    (procedure "run_yosys" line 22)
    invoked from within
"run_yosys"
    (procedure "run_synthesis" line 4)
    invoked from within
"run_synthesis"
    (procedure "run_non_interactive_mode" line 11)
    invoked from within
"run_non_interactive_mode {*}$argv"
    invoked from within
"if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } {
	puts_info "Running interactively"
	if { [info exists arg_values(-file)..."
    (file "/openLANE_flow/flow.tcl" line 164)
make: *** [Makefile:26: DFFRAM] Error 1

The "make pdk" currently only fetches the necessary files for one library variant, e.g. sky130_fd_sc_hd, but there seems to be no way to get the other libraries installed too

There are instances in which a user project may try to start on power up but the management SoC may not load the GPIO states until later. If the user project has not declared the GPIO defauts as needed for power up, then the user project could end up in an unrecoverable state.

The solution is to have a reset for the user project that can be applied independently of the reset to the management SoC, and which would be memory-mapped and also available in the housekeeping SPI. The program running from the management SoC could then hold the user project in reset until power supplies are reading stable and the GPIO state has been loaded.

Hi,
The generation of the DFFRAM macro fails during pdn generation. I know that rebuilding any macros from the non user area is not required. However, as I like to generate a similar macro for my user space area I started the build flow from within the openlane folder to study the build details. The build flow breaks with the following error log:

[INFO PDN-0016] Power Delivery Network Generator: Generating PDN
config: /project/openlane/DFFRAM/pdn.tcl
Error: pdn.tcl, 30 TypeError in method 'microns_to_dbu', argument 1 of type 'double'
[ERROR]: during executing: "openroad -exit /openlane/scripts/openroad/or_pdn.tcl |& tee >&@stdout /project/openlane/DFFRAM/runs/DFFRAM/logs/floorplan/7-pdn.log"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
child process exited abnormally

With the following call history:

"try_catch $::env(OPENROAD_BIN) -exit $::env(SCRIPTS_DIR)/openroad/or_pdn.tcl |& tee $::env(TERMINAL_OUTPUT) [index_file $::env(pdn_log_file_tag).log ..."
(procedure "gen_pdn" line 8)
invoked from within
"gen_pdn"
(procedure "run_power_grid_generation" line 94)
invoked from within
"run_power_grid_generation"
(procedure "run_floorplan" line 40)
invoked from within
"[lindex $step_exe 0] [lindex $step_exe 1] "
(procedure "run_non_interactive_mode" line 43)
invoked from within
"run_non_interactive_mode {*}$argv"
invoked from within
"if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } {
puts_info "Running interactively"
if { [info exists arg_values(-file)..."
(file "/openlane/flow.tcl" line 356)
make: *** [Makefile:43: DFFRAM] Error 1

I used the OpenLane and pdk versions as installed by the caravan Makefiles. Also building other macros results in the same error log. Any help is highly appreciated.

Stephan

1. Executing Verilog-2005 frontend: /openLANE_flow/designs/serv/src/test2.v
   Parsing SystemVerilog input from /openLANE_flow/designs/serv/src/test2.v' to AST representation. Generating RTLIL representation for module $paramod\serv_ctrl\RESET_STRATEGY=1296649801\RESET_PC=0\WITH_CSR=1'.
   Generating RTLIL representation for module \$paramod\serv_mem_if\WITH_CSR=1'. Generating RTLIL representation for module $paramod\serv_rf_if\WITH_CSR=1'.
   Generating RTLIL representation for module \$paramod\serv_state\RESET_STRATEGY=1296649801\WITH_CSR=1'. Generating RTLIL representation for module \serv_alu'.
   Generating RTLIL representation for module \serv_bufreg'. Generating RTLIL representation for module \serv_csr'.
   Generating RTLIL representation for module \serv_decode'. Generating RTLIL representation for module \serv_immdec'.
   Generating RTLIL representation for module `\serv_top'.
   Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: /openLANE_flow/designs/serv/src/serv_bufreg.v
   /openLANE_flow/designs/serv/src/serv_bufreg.v:1: ERROR: Re-definition of module `\serv_bufreg'!
   [ERROR]: during executing: "yosys -c /openLANE_flow/scripts/synth.tcl -l /openLANE_flow/designs/serv/runs/test_ex/logs/synthesis/yosys.log |& tee >&@stdout"
   [ERROR]: Exit code: 1
   [ERROR]: Last 10 lines:
   child process exited abnormally

[ERROR]: Please check yosys log file
[ERROR]: Dumping to /openLANE_flow/designs/serv/runs/test_ex/error.log

Hello, I am trying to run the design of caravel-OpenFPGA-EF but I cannot synthesize the design, and it shows the error message below:

13. Executing Verilog-2005 frontend: /openlane/designs/user_project_wrapper/src/sub_module/user_project_wrapper.v
/openlane/designs/user_project_wrapper/src/sub_module/user_project_wrapper.v:31: ERROR: Re-definition of module `\user_project_wrapper'!
child process exited abnormally

I realized the user_project_wrapper module has been redefined in the /sub_module/user_project_wrapper.v so I just remove the file, and ran the OpenLane again, but the error come out as following:

39.1. Analyzing design hierarchy..
ERROR: Module `\sky130_fd_sc_hd__ebufn_4' referenced in module `\user_project_wrapper' in cell `\FPGA2SOC_OUT_31_DEMUX_LA' is not part of the design.

I put the design .v files in the user_project_wrapper as shown the screenshots

OpenLane example files can work perfectly. I have been stuck due to this error for a long time but I still cannot find out what is wrong. Could anyone point me to the right direction to solve this issue? I will appreciate it!

Thanks!

Add a clock divider that allows very slow clock rates to the user projects.
this could be added to the user clock2.

I would like at least an 256 divider.

The storage module contains 2 instances of sram_1rw1r_32_256_8_sky130, SRAM_0 and SRAM_1.
SRAM_1 has unconnected inputs that are Hi-Z input to logic (particularly clk1 looks like it's input to an inverter).
Here is the verilog from verilog/rtl/storage.v

sram_1rw1r_32_256_8_sky130 SRAM_0 (
  .addr0(mgmt_addr),
  .addr1(mgmt_addr_ro),
  .clk0(mgmt_clk),
  .clk1(mgmt_clk),
  .csb0(mgmt_ena[0]),
  .csb1(mgmt_ena_ro),
  .din0(mgmt_wdata),
  .dout0(mgmt_rdata[31:0]),
  .dout1(mgmt_rdata_ro),
  .gnd(VGND),
  .vdd(VPWR),
  .web0(mgmt_wen[0]),
  .wmask0(mgmt_wen_mask[3:0])
 );
 sram_1rw1r_32_256_8_sky130 SRAM_1 (
  .addr0(mgmt_addr),
  .addr1({ _NC1, _NC2, _NC3, _NC4, _NC5, _NC6, _NC7, _NC8 }),
  .clk0(mgmt_clk),
  .csb0(mgmt_ena[1]),
  .din0(mgmt_wdata),
  .dout0(mgmt_rdata[63:32]),
  .dout1({ _NC9, _NC10, _NC11, _NC12, _NC13, _NC14, _NC15, _NC16, _NC17, _NC18, _NC19, _NC20, _NC21, _NC22, _NC23, _NC24, _NC25, _NC26, _NC27, _NC28, _NC29, _NC30, _NC31, _NC32, _NC33, _NC34, _NC35, _NC36, _NC37, _NC38, _NC39, _NC40 }),
  .gnd(VGND),
  .vdd(VPWR),
  .web0(mgmt_wen[1]),
  .wmask0(mgmt_wen_mask[7:4])
 );

You can notice that SRAM_1 is missing the following inputs

clk1
csb1

Also addr[0:7] are inputs defined as not connected. (edited)

The Caravel SOC design has one external interrupt pin, but doesn't seem to provide any accessible internal interrupt ports for internal wishbone slave peripheral user projects that would need them. It would be a shame to have to drive an extra output pin just to loop it back to the external interrupt input pin.

The content of checks/xor.log while running "make run-precheck"

First Layout: /home/s2s-svr1/projects/asic/trial/caravel_user_project/checks/user_project_wrapper_empty_erased.gds
Second Layout: /home/s2s-svr1/projects/asic/trial/caravel_user_project/checks/user_project_wrapper_erased.gds
Design Name: user_project_wrapper
Output GDS will be: /home/s2s-svr1/projects/asic/trial/caravel_user_project/checks/user_project_wrapper.xor.gds
Reading /home/s2s-svr1/projects/asic/trial/caravel_user_project/checks/user_project_wrapper_empty_erased.gds ..
ERROR: In /usr/local/bin/xor_checks/xor.drc: Stream has unknown format: /home/s2s-svr1/projects/asic/trial/caravel_user_project/checks/user_project_wrapper_empty_erased.gds in Layout::read
ERROR: Stream has unknown format: /home/s2s-svr1/projects/asic/trial/caravel_user_project/checks/user_project_wrapper_empty_erased.gds in Layout::read in MacroInterpreter::execute
/usr/local/bin/xor_checks/xor.drc:15:in execute_drc' :/built-in-macros/drc_interpreters.lym:18:in instance_eval'
:/built-in-macros/drc_interpreters.lym:18:in execute_drc' :/built-in-macros/drc_interpreters.lym:92:in execute'

The mgmt_protect_hv.v of the Buffer Protection contains a section to emulate the substrate shortening ground together, which was introduced with 4d78284.

assign vssa2 = vssa1;
assign vssa1 = vssd;

It is stated to be required for LVS.

In all testbenches there is only one source of ground, wire VSS = 1'b0;. In simulators other than iverilog (i.a. Questa/Modelsim) this and the above assignment will result in an undefined behavior, since the signal is essentially assigned to itself multiple times.

There are two possible solutions:

1. Defining separate ground signals in the testbenches (Although in reality it is most probably the same ground?)
2. Exclude this part from simulations since it is stated to be required for LVS only. This could be done like this

`ifndef SIM
    assign vssa2 = vssa1;
    assign vssa1 = vssd;
`endif

Note, this is not reproducible with iverilog!