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al-folio

A beautiful, simple, clean, and responsive Jekyll theme for academics

apot_quantization

PyTorch implementation for the APoT quantization (ICLR 2020)

ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.9, working as a coprocessor to CORE-V's CVA6 core

awesome-semiconductor-startups

List of awesome semiconductor startups

bart-system-verification

This repository contains the BART (Bay Area Rapid Transit) system model and Implementation code for ARM CortexM series. Formal models are presented in AutoFocus3(AF3) format in which you can verify the properties using NuSMV model checker.

barvinn

BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/

basechiselproj

This is a simple chisel project

berkeley-hardfloat

bluetoothterminal

You can monitor sensor data through Bluetooth socket.

chisel-float

Floating point modules for CHISEL

chisel-tutorial

chisel tutorial exercises and answers

chisel-tutorial-wiki

chisel tutorial wiki (modified)

chisel3

Chisel 3

chisel_projects

common_cells

Common SystemVerilog components

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux. Refer to https://github.com/openhwgroup/cva6

dnn-gating

docker-riscv

A Dockerfile for the tools needed to develop for the RISC-V open-source CPU

ele8307

fft

fpga-zynq

Support for Rocket Chip on Zynq FPGAs

frdm-kl25z-spi-driver

FRDM KL25Z SPI Driver

freedom

Source files for SiFive's Freedom platforms

freedom-e-sdk

Open Source Software for Developing on the Freedom E Platform

functionalprogramming

My solutions for Functional Programming with Scala course offered in Coursera

fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

fusesoc-cores

FuseSoC standard core library

gol

gradoverride

A complete PyTorch experiment skeleton

hossein1387.github.io

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