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Vitis Libraries

Home Page: https://docs.xilinx.com/r/en-US/Vitis_Libraries

License: Apache License 2.0

C++ 53.65% Makefile 32.81% Tcl 2.47% Shell 0.07% Python 1.01% CSS 0.01% Lua 0.15% C 9.72% Perl 0.09% Roff 0.01% Cuda 0.01% SWIG 0.01% Hack 0.01% CMake 0.01%

vitis_libraries's Introduction

Vitis Accelerated Libraries

Vitis™ Unified Software Platform includes an extensive set of open-source, performance-optimized libraries that offer out-of-the-box acceleration with minimal to zero-code changes to your existing applications.

Comprehensive documentation

Common Vitis accelerated-libraries for Math, Statistics, Linear Algebra, and DSP offer a set of core functionality for a wide range of diverse applications.
Domain-specific Vitis accelerated libraries offer out-of-the-box acceleration for workloads like Vision and Image Processing, Quantitative Finance, Database, and Data Analytics, Data Compression and more.
Leverage the rich growing ecosystem of partner-accelerated libraries, framework plug-ins, and accelerated applications to hit the ground running and accelerate your path to production.

Use in Familiar Programming Languages

Use Vitis accelerated-libraries in commonly-used programming languages that you know like C, C++, and Python. Leverage Xilinx platforms as an enabler in your applications – Work at an application level and focus your core competencies on solving challenging problems in your domain, accelerate time to insight, and innovate.

Whether you want to accelerate portions of your existing x86 host application code or want to develop accelerators for deployment on Xilinx embedded platforms, calling a Vitis accelerated-library API or Kernel in your code offers the same level of abstraction as any software library.

Scalable and Flexible

Vitis accelerated-libraries are accessible to all developers through GitHub and scalable across all Xilinx platforms. Develop your applications using these optimized libraries and seamlessly deploy across Xilinx platforms at the edge, on-premise or in the cloud without having to reimplement your accelerated application.

For rapid prototyping and quick evaluation of the benefits Xilinx can bring to your applications, you can use them as plug-and-play accelerators, called directly as an API in the user application for several workloads like Computer Vision and Image Processing, Quantitative Finance, Database, and Data Analytics among others.

To design custom accelerators for your application, use Vitis library functions as optimized algorithmic building blocks, modify them to suit your specific needs, or use them as a reference to completely design your own. Choose the flexibility you need!

Combine domain-specific Vitis libraries with pre-optimized deep learning models from the Vitis AI library or the Vitis AI development kit to accelerate your whole application and meet the overall system-level functionality and performance goals.

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vitis_libraries's Issues

bug in xf::cv::cvMat2AXIvideoxf function

Hi,
I'm trying to use the xf::cv::cvMat2AXIvideoxf function in my test bench for debugging purpose and it seems like the whole
xf_axi.hpp file has problems and doesn't compile at all. Are there any files i need to include before this file or is this actually a bug not letting the code to even compile?

here is a link to my exact issue in xilinx forums:
https://forums.xilinx.com/t5/High-Level-Synthesis-HLS/Vitis-Vision-library-xf-cv-cvMat2AXIvideoxf-problem/m-p/1142291#M21590

dsp FFT has no L2 Benchmarks?

document https://github.com/Xilinx/Vitis_Libraries/blob/master/dsp/docs/src/benchmarks/L2_fft_benchmark.rst say:
List of Benchmarks
To the run the benchmarks user has to checkin the Xilinx Vitis libraries. Go to dsp/L2/benchmarks/FPGA folder which contains the Vitis FFT benchmarks. This folder contains different benchmarks for 1D and 2D FFTs as shown below:

1dFix : 1D Fix Point FFT Benchmark
1dFloat : 1D Floating Point FFT Benchmark
2dFix : 2D Fix Point FFT Benchmark
2dFloat : 2D Floating Point FFT Benchmark
Building and Running the Benchmarks

but at github ,the vitis_libraries has no FFT L2 benchmarks,where can I download the FFT L2 benchmarks?or When will Xilinx release the FFT L2 benchmarks?
Thanks!

xilLz4CompressStream outputs no more than 4.1KBytes

I'm trying to utilize xilLz4CompressStream as part of my kernel. When the input size is large to some extent (I have not found the certain threshold), the output size will be 4.1KBytes. This behaviour is conformed by putting both a 98KBytes text and its first 49KBytes half but achieving the same two 4.1KBytes outputs (the sameness is conformed with diff). In addition, xilLz4CompressStream consumes the 'extra' inputs correctly (though not generating the corresponding outputs), i.e. the previous stages in the dataflow does not stall due to this behaviour.

This behaviour is found in software emulation, hardware emulation and true hardware. When this behaviour is observed, though the results of hardware emulation and true hardware are the same (confirmed by diff), the results of software emulation and hardware emulation (also the hardware) differ.

p.s. To let the core outputs only after receiving some input, I removed the HLS RESOURCE pragmas.

Issue with common/xf_axi_sdata.hpp file

Hi,
I've noticed that when I use the structs defined in the "xf_axi_sdata.hpp" file in the Interfaces of my IP core, the HLS synthesis tool doesn't synthesis the interface properly. But when instead I use the same structs from the "ap_axi_sdata.h" file it works properly, I cannot see any difference in the codes of these structs but somehow the ones from xf_axi_sdata.hpp don't get synthesized correctly.
Here is an example of a synthesized axis interface using the xf_axi_sdata.hpp file structs:

Here is the same interface using the ap_axi_sdata.h file structs:

(the interface must have a 192 bit data width and a 1 bit tuser, tid and tdest data width)

/usr/lib/libgdal.so.20: undefined reference to `xmlXPathRegisterNs@LIBXML2_2.4.30' /usr/lib/x86_64-linux-gnu/libspatialite.so.7: undefined reference to `xmlNanoHTTPCleanup@LIBXML2_2.4.30'

I have trying to test compiling Vitis_Libraries/vision/L1/examples/sgbm with the following bash scripts and got numerous undefined errors.
eli@elli-A17-R4:~/gitee/Vitis_Libraries/vision/L1/examples/sgbm$ cat runme.sh

#! /bin/bash
source /tools/Xilinx/Vitis/2020.1/settings64.sh
source /opt/xilinx/xrt/setup.sh
export DEVICE=/opt/xilinx/platforms/xilinx_u200_xdma_201830_2/xilinx_u200_xdma_201830_2.xpfm
export OPENCV_INCLUDE=/usr/include/opencv2
export OPENCV_LIB=/usr/lib/x86_64-linux-gnu
export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$OPENCV_LIB
make run CSIM=1 XPART='xcu200-fsgd2104-2-e' BOARD=Zynq ARCH=aarch64
#make run CSIM=1 BOARD=Zynq ARCH=aarch64

As the version of libxml2 in Ubuntu Bionic 18.04 should be 2.9.4+dfsg1-6.1ubuntu1.3, where is the version of LIBXML2_2.4.30 that the errors messages are referring to?

eli@elli-A17-R4:~/gitee/Vitis_Libraries/vision/L1/examples/sgbm$ ./runme.sh
XILINX_XRT : /opt/xilinx/xrt
PATH : /opt/xilinx/xrt/bin:/tools/Xilinx/Vitis/2020.1/bin:/tools/Xilinx/Vitis/2020.1/gnu/microblaze/lin/bin:/tools/Xilinx/Vitis/2020.1/gnu/arm/lin/bin:/tools/Xilinx/Vitis/2020.1/gnu/microblaze/linux_toolchain/lin64_le/bin:/tools/Xilinx/Vitis/2020.1/gnu/aarch32/lin/gcc-arm-linux-gnueabi/bin:/tools/Xilinx/Vitis/2020.1/gnu/aarch32/lin/gcc-arm-none-eabi/bin:/tools/Xilinx/Vitis/2020.1/gnu/aarch64/lin/aarch64-linux/bin:/tools/Xilinx/Vitis/2020.1/gnu/aarch64/lin/aarch64-none/bin:/tools/Xilinx/Vitis/2020.1/gnu/armr5/lin/gcc-arm-none-eabi/bin:/tools/Xilinx/Vitis/2020.1/tps/lnx64/cmake-3.3.2/bin:/tools/Xilinx/Vitis/2020.1/cardano/bin:/tools/Xilinx/Vivado/2020.1/bin:/tools/Xilinx/DocNav:/home/eli/.bin_:/usr/local/cuda/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin
LD_LIBRARY_PATH : /opt/xilinx/xrt/lib:
PYTHONPATH : /opt/xilinx/xrt/python:
Configured: settings.tcl

set XPART xcu200-fsgd2104-2-e
set CSIM 1
set CSYNTH 0
set COSIM 0
set VIVADO_SYN 0
set VIVADO_IMPL 0
set XF_PROJ_ROOT "/home/eli/gitee/Vitis_Libraries/vision/"
set OPENCV_INCLUDE "/usr/include/opencv2"
set OPENCV_LIB "/usr/lib/x86_64-linux-gnu"
set CUR_DIR "/home/eli/gitee/Vitis_Libraries/vision/L1/examples/sgbm"

vitis_hls -f run_hls.tcl;

****** Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.1.1 (64-bit)
**** SW Build 2960000 on Wed Aug 5 22:57:21 MDT 2020
**** IP Build 2956692 on Thu Aug 6 01:41:30 MDT 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source /tools/Xilinx/Vitis/2020.1/scripts/vitis_hls/hls.tcl -notrace
INFO: [HLS 200-10] Running '/tools/Xilinx/Vitis/2020.1/bin/unwrapped/lnx64.o/vitis_hls'
INFO: [HLS 200-10] For user 'eli' on host 'elli-A17-R4' (Linux_x86_64 version 5.4.0-52-generic) on Thu Oct 22 14:02:26 CST 2020
INFO: [HLS 200-10] On os Ubuntu 18.04.5 LTS
INFO: [HLS 200-10] In directory '/home/eli/gitee/Vitis_Libraries/vision/L1/examples/sgbm'
Sourcing Tcl script 'run_hls.tcl'
INFO: [HLS 200-10] Opening and resetting project '/home/eli/gitee/Vitis_Libraries/vision/L1/examples/sgbm/sgbm.prj'.
WARNING: [HLS 200-40] No /home/eli/gitee/Vitis_Libraries/vision/L1/examples/sgbm/sgbm.prj/sol1/sol1.aps file found.
INFO: [HLS 200-10] Adding design file '/home/eli/gitee/Vitis_Libraries/vision//L1/examples/sgbm/xf_sgbm_accel.cpp' to the project
INFO: [HLS 200-10] Adding test bench file '/home/eli/gitee/Vitis_Libraries/vision//L1/examples/sgbm/xf_sgbm_tb.cpp' to the project
INFO: [HLS 200-10] Creating and opening solution '/home/eli/gitee/Vitis_Libraries/vision/L1/examples/sgbm/sgbm.prj/sol1'.
INFO: [HLS 200-10] Cleaning up the solution database.
WARNING: [HLS 200-40] No /home/eli/gitee/Vitis_Libraries/vision/L1/examples/sgbm/sgbm.prj/sol1/sol1.aps file found.
INFO: [HLS 200-1505] Using default flow_target 'vivado'
Resolution: For help on HLS 200-1505 see www.xilinx.com/html_docs/xilinx2020_1/hls-guidance/200-1505.html
INFO: [HLS 200-10] Setting target device to 'xcu200-fsgd2104-2-e'
INFO: [SYN 201-201] Setting up clock 'default' with a period of 3.3ns.
INFO: [SIM 211-2] *************** CSIM start ***************
INFO: [SIM 211-4] CSIM will launch GCC as the compiler.
make[1]: Entering directory '/home/eli/gitee/Vitis_Libraries/vision/L1/examples/sgbm/sgbm.prj/sol1/csim/build'
Compiling ../../../../xf_sgbm_tb.cpp in debug mode
Compiling ../../../../xf_sgbm_accel.cpp in debug mode
Generating csim.exe
Makefile.rules:379: recipe for target 'csim.exe' failed
make[1]: Leaving directory '/home/eli/gitee/Vitis_Libraries/vision/L1/examples/sgbm/sgbm.prj/sol1/csim/build'
/usr/lib/libgdal.so.20: undefined reference to xmlBufferFree@LIBXML2_2.4.30' /usr/lib/libgdal.so.20: undefined reference to xmlBufferCreate@LIBXML2_2.4.30'
/usr/lib/libgdal.so.20: undefined reference to xmlXPathRegisterNs@LIBXML2_2.4.30' /usr/lib/x86_64-linux-gnu/libspatialite.so.7: undefined reference to xmlNanoHTTPCleanup@LIBXML2_2.4.30'
/usr/lib/x86_64-linux-gnu/libdap.so.25: undefined reference to xmlTextWriterEndElement@LIBXML2_2.6.0' /usr/lib/x86_64-linux-gnu/libspatialite.so.7: undefined reference to xmlSearchNs@LIBXML2_2.4.30'
/usr/lib/x86_64-linux-gnu/libdap.so.25: undefined reference to xmlCreateFileParserCtxt@LIBXML2_2.4.30' /usr/lib/x86_64-linux-gnu/libdap.so.25: undefined reference to xmlBufferCreateSize@LIBXML2_2.4.30'
/usr/lib/libgdal.so.20: undefined reference to xmlSchemaSetValidErrors@LIBXML2_2.5.8' /usr/lib/x86_64-linux-gnu/libtbb.so.2: undefined reference to __cxa_init_primary_exception@CXXABI_1.3.11'
/usr/lib/x86_64-linux-gnu/libspatialite.so.7: undefined reference to xmlAddNextSibling@LIBXML2_2.4.30' /usr/lib/libgdal.so.20: undefined reference to xmlXPathNewContext@LIBXML2_2.4.30'
/usr/lib/x86_64-linux-gnu/libspatialite.so.7: undefined reference to xmlSetGenericErrorFunc@LIBXML2_2.4.30' /usr/lib/libgdal.so.20: undefined reference to xmlXPathNewString@LIBXML2_2.4.30'
/usr/lib/libgdal.so.20: undefined reference to xmlBufferContent@LIBXML2_2.4.30' /usr/lib/x86_64-linux-gnu/libdap.so.25: undefined reference to xmlTextWriterStartElementNS@LIBXML2_2.6.0'
/usr/lib/x86_64-linux-gnu/libspatialite.so.7: undefined reference to xmlAddPrevSibling@LIBXML2_2.4.30' /usr/lib/x86_64-linux-gnu/libdap.so.25: undefined reference to xmlTextWriterSetIndentString@LIBXML2_2.6.5'
/usr/lib/x86_64-linux-gnu/libspatialite.so.7: undefined reference to xmlAddChild@LIBXML2_2.4.30' /usr/lib/libgdal.so.20: undefined reference to xmlCatalogResolveURI@LIBXML2_2.4.30'
/usr/lib/libgdal.so.20: undefined reference to xmlSchemaNewMemParserCtxt@LIBXML2_2.5.8' /usr/lib/x86_64-linux-gnu/libtbb.so.2: undefined reference to std::__exception_ptr::exception_ptr::exception_ptr(void*)@CXXABI_1.3.11'
/usr/lib/x86_64-linux-gnu/libdap.so.25: undefined reference to xmlCheckVersion@LIBXML2_2.4.30' /usr/lib/x86_64-linux-gnu/libspatialite.so.7: undefined reference to xmlSetNs@LIBXML2_2.4.30'
/usr/lib/x86_64-linux-gnu/libdap.so.25: undefined reference to xmlTextWriterEndDocument@LIBXML2_2.6.0' /usr/lib/x86_64-linux-gnu/libspatialite.so.7: undefined reference to xmlNewText@LIBXML2_2.4.30'
/usr/lib/libgdal.so.20: undefined reference to xmlSchemaSetParserErrors@LIBXML2_2.5.8' /usr/lib/x86_64-linux-gnu/libdap.so.25: undefined reference to xmlTextWriterWriteString@LIBXML2_2.6.0'
/usr/lib/libgdal.so.20: undefined reference to xmlSchemaValidateFile@LIBXML2_2.6.20' /usr/lib/x86_64-linux-gnu/libdap.so.25: undefined reference to xmlBufferSetAllocationScheme@LIBXML2_2.4.30'
/usr/lib/libgdal.so.20: undefined reference to xmlSchemaParse@LIBXML2_2.5.8' /usr/lib/libgdal.so.20: undefined reference to xmlXPathEvalExpression@LIBXML2_2.4.30'
/usr/lib/x86_64-linux-gnu/libspatialite.so.7: undefined reference to xmlReadFile@LIBXML2_2.6.0' /usr/lib/x86_64-linux-gnu/libdap.so.25: undefined reference to xmlParseDocument@LIBXML2_2.4.30'
/usr/lib/libgdal.so.20: undefined reference to xmlGetExternalEntityLoader@LIBXML2_2.4.30' /usr/lib/x86_64-linux-gnu/libspatialite.so.7: undefined reference to xmlFreeNode@LIBXML2_2.4.30'
/usr/lib/libgdal.so.20: undefined reference to xmlXPathErr@LIBXML2_2.6.0' /usr/lib/libgdal.so.20: undefined reference to xmlXPathFreeContext@LIBXML2_2.4.30'
/usr/lib/x86_64-linux-gnu/libdap.so.25: undefined reference to xmlTextWriterEndPI@LIBXML2_2.6.0' /usr/lib/libgdal.so.20: undefined reference to xmlXPathFreeObject@LIBXML2_2.4.30'
/usr/lib/libgdal.so.20: undefined reference to xmlNodeDump@LIBXML2_2.4.30' /usr/lib/libgdal.so.20: undefined reference to xmlSchemaNewValidCtxt@LIBXML2_2.5.8'
/usr/lib/x86_64-linux-gnu/libspatialite.so.7: undefined reference to xmlXPathFreeCompExpr@LIBXML2_2.4.30' /usr/lib/x86_64-linux-gnu/libspatialite.so.7: undefined reference to xmlXPathCompile@LIBXML2_2.4.30'
/usr/lib/libgdal.so.20: undefined reference to xmlXPathRegisterFunc@LIBXML2_2.4.30' /usr/lib/x86_64-linux-gnu/libspatialite.so.7: undefined reference to xmlReplaceNode@LIBXML2_2.4.30'
/usr/lib/libgdal.so.20: undefined reference to valuePush@LIBXML2_2.4.30' /usr/lib/x86_64-linux-gnu/libdap.so.25: undefined reference to xmlTextWriterWriteRaw@LIBXML2_2.6.0'
/usr/lib/x86_64-linux-gnu/libdap.so.25: undefined reference to xmlTextWriterWriteElement@LIBXML2_2.6.0' /usr/lib/libgdal.so.20: undefined reference to xmlSchemaValidateDoc@LIBXML2_2.5.8'
/usr/lib/x86_64-linux-gnu/libdap.so.25: undefined reference to xmlCreatePushParserCtxt@LIBXML2_2.4.30' /usr/lib/libgdal.so.20: undefined reference to xmlXPathBooleanFunction@LIBXML2_2.4.30'
/usr/lib/x86_64-linux-gnu/libspatialite.so.7: undefined reference to xmlSearchNsByHref@LIBXML2_2.4.30' /usr/lib/libgdal.so.20: undefined reference to xmlGetLastError@LIBXML2_2.6.0'
/usr/lib/x86_64-linux-gnu/libdap.so.25: undefined reference to xmlParseChunk@LIBXML2_2.4.30' /usr/lib/x86_64-linux-gnu/libdap.so.25: undefined reference to xmlTextWriterWriteAttribute@LIBXML2_2.6.0'
/usr/lib/libgdal.so.20: undefined reference to xmlParseDoc@LIBXML2_2.4.30' /usr/lib/x86_64-linux-gnu/libspatialite.so.7: undefined reference to xmlSchemaNewDocParserCtxt@LIBXML2_2.6.2'
/usr/lib/x86_64-linux-gnu/libspatialite.so.7: undefined reference to xmlCleanupParser@LIBXML2_2.4.30' /usr/lib/x86_64-linux-gnu/libdap.so.25: undefined reference to xmlNewTextWriterMemory@LIBXML2_2.6.0'
/usr/lib/x86_64-linux-gnu/libspatialite.so.7: undefined reference to xmlDocDumpFormatMemory@LIBXML2_2.4.30' /usr/lib/libgdal.so.20: undefined reference to valuePop@LIBXML2_2.4.30'
/usr/lib/libgdal.so.20: undefined reference to xmlSetExternalEntityLoader@LIBXML2_2.4.30' /usr/lib/x86_64-linux-gnu/libdap.so.25: undefined reference to xmlTextWriterStartPI@LIBXML2_2.6.0'
/usr/lib/x86_64-linux-gnu/libdap.so.25: undefined reference to xmlSAX2GetLineNumber@LIBXML2_2.6.0' /usr/lib/libgdal.so.20: undefined reference to xmlNewStringInputStream@LIBXML2_2.4.30'
/usr/lib/x86_64-linux-gnu/libdap.so.25: undefined reference to xmlTextWriterStartElement@LIBXML2_2.6.0' /usr/lib/libgdal.so.20: undefined reference to xmlFree@LIBXML2_2.4.30'
/usr/lib/libgdal.so.20: undefined reference to xmlSchemaFree@LIBXML2_2.5.8' /usr/lib/x86_64-linux-gnu/libdap.so.25: undefined reference to xmlTextWriterSetIndent@LIBXML2_2.6.5'
/usr/lib/libgdal.so.20: undefined reference to xmlSchemaFreeParserCtxt@LIBXML2_2.5.8' /usr/lib/x86_64-linux-gnu/libdap.so.25: undefined reference to xmlTextWriterStartDocument@LIBXML2_2.6.0'
/usr/lib/libgdal.so.20: undefined reference to xmlDocGetRootElement@LIBXML2_2.4.30' /usr/lib/libgdal.so.20: undefined reference to xmlFreeDoc@LIBXML2_2.4.30'
/usr/lib/libgdal.so.20: undefined reference to xmlCatalogResolveSystem@LIBXML2_2.4.30' /usr/lib/libgdal.so.20: undefined reference to xmlSchemaFreeValidCtxt@LIBXML2_2.5.8'
/usr/lib/x86_64-linux-gnu/libspatialite.so.7: undefined reference to xmlInitParser@LIBXML2_2.4.30' /usr/lib/x86_64-linux-gnu/libdap.so.25: undefined reference to xmlFreeParserCtxt@LIBXML2_2.4.30'
/usr/lib/x86_64-linux-gnu/libspatialite.so.7: undefined reference to xmlNewNs@LIBXML2_2.4.30' /usr/lib/x86_64-linux-gnu/libspatialite.so.7: undefined reference to xmlNewNode@LIBXML2_2.4.30'
/usr/lib/x86_64-linux-gnu/libspatialite.so.7: undefined reference to xmlReadMemory@LIBXML2_2.6.0' /usr/lib/x86_64-linux-gnu/libdap.so.25: undefined reference to xmlFreeTextWriter@LIBXML2_2.6.0'
/usr/lib/x86_64-linux-gnu/libdap.so.25: undefined reference to `xmlGetPredefinedEntity@LIBXML2_2.4.30'
collect2: error: ld returned 1 exit status
make[1]: *** [csim.exe] Error 1
ERROR: [SIM 211-100] 'csim_design' failed: compilation error(s).
INFO: [SIM 211-3] *************** CSIM finish ***************
4
while executing
"source run_hls.tcl"
("uplevel" body line 1)
invoked from within
"uplevel #0 [list source $arg] "

INFO: [Common 17-206] Exiting vitis_hls at Thu Oct 22 14:02:34 2020...
Makefile:251: recipe for target 'runhls' failed
make: *** [runhls] Error 1

Missing semicolon on line 27 of xf_fintech_cf_black_scholes.cpp

line 27 is missing a semicolon:
https://github.com/Xilinx/Vitis_Libraries/blob/master/quantitative_finance/L3/tests/CFBlackScholes/xf_fintech_cf_black_scholes.cpp

Vitis Libraries GUI flow

Hello,
Thanks for the work on the libraries.
I am using the makefile flow and it works perfectly, though I would try to use the debugger for exploiting the libraries for a different project.
Hence, I am wondering if there is any documentation or standard way to test Viti libraries through the GUI, because I experienced several issues in reapplying the make variables.
Is it?

Thank you very much

bug in xf::cv::AXIvideo2xfMat

Hi,
I'm trying to use xf::cv::AXIvideo2xfMat and there seem to be a bug inside the code causing the synthesizer to error.
the error is as followed:

ERROR: [HLS 200-977] Argument 'stream_in_1_V' failed dataflow checking: it can only be used in one process.
WARNING: [HLS 200-992] Argument 'stream_in_1_V' has read operations in process function 'Loop_loop_wait_for_start_proc26'.
Resolution: For help on HLS 200-992 see www.xilinx.com/html_docs/xilinx2020_1/hls-guidance/200-992.html
WARNING: [HLS 200-992] Argument 'stream_in_1_V' has read operations in process function 'Loop_loop_height_proc'.
Resolution: For help on HLS 200-992 see www.xilinx.com/html_docs/xilinx2020_1/hls-guidance/200-992.html

I think it is because the stream input is being read in two different loops in the function code in xf_infra.hpp file. (loop_wait_for_start and loop_height)

a link to this problem in Xilinx forums:
https://forums.xilinx.com/t5/High-Level-Synthesis-HLS/HLS-failed-dataflow-checking/td-p/1049741
can you please fix this issue cause I really need this function for my work.

thanks
Ali

Issue with structs file

Hello! I stuck with this error

../home/l/vitis2020.1/Vitis_Libraries-master/vision/L1/include/common/xf_structs.hpp:778:44: error: 'xf::cv::Mat<3, 1080, 1920, 1>::DATATYPE' {aka 'struct ap_uint<32>'} has no member named 'chnl'
778 | data[r * packcols + c].chnl[p][ch] = in_val;

Is this an issue related to inclusion of headers ? or something else?

Thanks in advance!

Vitis Vision documentation link is incorrect

The link to the Vitis Vision documentation in vision/README.md is incorrect. It should point to:

https://xilinx.github.io/Vitis_Libraries/vision/2020.1/index.html

Vitis_Libraries/vision/L2/ Makefile does unnecessary check for embedded targets

Instructions at the following README specify env-vars for PCIe vs embedded:

https://github.com/Xilinx/Vitis_Libraries/tree/master/vision/L2#commands-to-run

But when attempting to make for an embedded target the Makefile fails due to the PCIe env-vars missing. Tested with https://github.com/Xilinx/Vitis_Libraries/blob/master/vision/L2/examples/resize/Makefile but maybe applies to other examples as well.

Workaround was simple:

export OPENCV_INCLUDE=0
export OPENCV_LIB=0

Question about Vitis SPARSE library

Hello. I am studying the Sparse (CSC) implementation of Vitis Accelerated Libraries.

From here, I understand that for Alveo U280, we want the 2 readWriteHbm CUs need to be placed in SLR0, so that they have direct connectivity with the available HBM channels.

I have also read, that we want the Compute Units that access HBM channels to reside in the SLR that is directly connected with them, therefore SLR0 in Alveo U280 (and Alveo U50 too).

However, reading the configuration files here, I noticed that readWriteHbm_0 is placed in SLR0 and readWriteHbm_1 is placed in SLR1. Is there any reason that this is written like this? I understand that you want each readWriteHbm to be "close" to the cscRow CUs that are assigned to them, but in this configuration there is an SLR crossing (readWriteHbm_1 -> HBM Channels), that, from what I have read, we want to avoid as much as possible.

What of the 2 is correct? Put both readWriteHbms in SLR0, close to HBM channels, or it doesn't make much of a difference to place them elsewhere ?

Thank you!

Makefile 2020.1

If embedded XPLATFORM selection is different than zcu102 and zcu104, there is no LDFLAGS assigned. Could embedded platforms be more generically specified within makefile?

Makefile lines 127-148

ifeq ($(HOST_ARCH), x86) LDFLAGS += -L$(XILINX_VIVADO)/lnx64/tools/fpo_v7_0 -Wl,--as-needed -lgmp -lmpfr -lIp_floating_point_v7_0_bitacc_cmodel endif ifneq (,$(shell echo $(XPLATFORM) | awk '/u200/')) CXXFLAGS += -I$(OPENCV_INCLUDE) LDFLAGS += -L$(OPENCV_LIB) else ifneq (,$(shell echo $(XPLATFORM) | awk '/zcu102/')) CXXFLAGS += -I$(SYSROOT)/usr/include CXXFLAGS += --sysroot=$(SYSROOT) LDFLAGS += -L$(SYSROOT)/usr/lib LDFLAGS += -L${SYSROOT}/opt/xilinx/xrt/lib else ifneq (,$(shell echo $(XPLATFORM) | awk '/u50/')) CXXFLAGS += -I$(OPENCV_INCLUDE) LDFLAGS += -L$(OPENCV_LIB) else ifneq (,$(shell echo $(XPLATFORM) | awk '/zcu104/')) CXXFLAGS += -I$(SYSROOT)/usr/include CXXFLAGS += --sysroot=$(SYSROOT) LDFLAGS += -L$(SYSROOT)/usr/lib LDFLAGS += -L${SYSROOT}/opt/xilinx/xrt/lib endif

[XRT] No device found during compiling LZ4 L2

Hi,

I'm trying to generate the bitstream file with files in lz4 l2.
Compiling sw_emu/hw_emu are both fine.
But after I set the target as hw, it gives "[XRT] No device found" error message.
The board that I'm using is U250 and it can be found either lspci and xbmgmt scan.
Is there any possible way to fix it?

Thanks,

hls::erf and hls::erfc not linking in hw_emu

When I replace calls to hls::erf and hls::ercf with hls::exp everything works fine.

I have attached the logs.
v++.log
link.steps.log

Are there any examples of using local or URL link video decoding?

Missing env-var in Vitis_Libraries/vision/L2 > For embedded devices instructions

As of 2020.1 the generated image now also requires:

export XILINX_XRT=/usr

Before the app can be run.

Contradictory information in DSP documentation

In https://xilinx.github.io/Vitis_Libraries/dsp/user_guide/L1.html section "Start with floating point model" (direct link https://xilinx.github.io/Vitis_Libraries/dsp/user_guide/L1.html#start-with-floating-point-model) there are two lines for the complex_wrapper<float> type, one saying Synthesis is supported and one saying not. I assume one of these should be complex_wrapper<double> ?

Document differences between hash_join_v3_sc and hash_join_v3_bp

Would be great if you could document a description on the differences between the *sc and *bp versions of the hash_join_v3 tests found in the Vitis_Libraries/database/L1/tests/hw folder: https://github.com/Xilinx/Vitis_Libraries/tree/master/database/L1/tests/hw

SSR FFT example 1dfix_impulse will not synthesize

Vitis_Libraries/dsp/L1/examples/1Dfix_impluse requires alteration of hls_ssr_fft_parallel_fft_kernel.hpp before it will synthesize. See https://forums.xilinx.com/t5/High-Level-Synthesis-HLS/Synthesis-hangs-in-HLS-2019-2-1-on-SSR-FFT-example/m-p/1060615 for details.

SVD benchmark reads xclbin filename from env, not -xclbin

host.exe checks for xclbin name from environment variable

Vitis_Libraries/quantitative_finance/L1/benchmarks/SVD/src/main.cpp

Line 21 in 40b98f7

std::string xclbinName = read_verify_env_string("XCLBINNAME");

However, instructions indicate xclbin should be passed as parameter:
https://github.com/Xilinx/Vitis_Libraries/tree/master/quantitative_finance/L1/benchmarks/SVD

Alveo U50 support

Please, add U50 support

How to use Vitis_Database_Library with SQL-engine

I understand that if I want to use database libraries with PostgreSQL, I need to be columnar.

Therefore, if I use cstore_fdw, an OSS from citusDB, I can treat PostgreSQL as a column-oriented table. Is it possible to use a database library in this configuration?

Also, please let us know if you have a recommended SQL-engine that is supposed to use the database library.

Generate "compression_only" and "decompression_only" - xclbin for Lz4 in L2

make all TARGET=hw DEVICE=xilinx_u200_xdma_201830_2
after this hardware compile execution, under ./build/xclbin*/ , found only compress_decompress.xclbin

How to generate bitstream for compress_only & decompress_only, What are the arguments should be enabled to get this? or what modification I should make? Please let me know.

database/L1/benchmarks/.. IP cannot be compiled on Alveo U250

the src code and conn_250.ini file uses more DRAM banks than U250 actually supported (4).

How to use vitis libraries on ZCU102

I noticed that all vitis libraries can only use on Alveo U200 or U250. How can I use them on ZCU102? Is there any documents I can refer to?

error while building the rtm2d example from the Vitis Libraries

while building the rtm2d example, taken from the Vitis hpc libraries, I got an error.

I use the vitis 2020.2 version and from the VITIS_LIBRARY_FOLDER/hpc/L2/tests/rtm2d/rtm/ folder I gave the following command

make build TARGET=hw DEVICE=xilinx_u280_xdma_201920_3

after a while, I got the following error:

INFO: [Project 1-461] DRC finished with 1395 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
ERROR: [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run.

Time (s): cpu = 00:01:02 ; elapsed = 00:00:40 . Memory (MB): peak = 10738.539 ; gain = 0.000 ; free physical = 23673 ; free virtual = 81946
INFO: [Common 17-83] Releasing license: Implementation
172 Infos, 503 Warnings, 7 Critical Warnings and 101 Errors encountered.
opt_design failed
opt_design: Time (s): cpu = 00:01:03 ; elapsed = 00:00:41 . Memory (MB): peak = 10738.539 ; gain = 0.000 ; free physical = 23673 ; free virtual = 81946
ERROR: [Common 17-39] 'opt_design' failed due to earlier errors.

INFO: [Common 17-206] Exiting Vivado at Tue Dec 15 14:43:10 2020...
[Tue Dec 15 14:43:11 2020] impl_1 finished
WARNING: [Vivado 12-8222] Failed run(s) : 'impl_1'
wait_on_run: Time (s): cpu = 00:00:14 ; elapsed = 00:23:16 . Memory (MB): peak = 5724.684 ; gain = 0.000 ; free physical = 23690 ; free virtual = 81967
INFO: [OCL_UTIL] internal step: log_generated_reports for implementation 'output/generated_reports.log'
INFO: [OCL_UTIL] internal step: problem implementing dynamic region, impl_1: opt_design ERROR
INFO: [OCL_UTIL] status: fail (opt_design ERROR)
INFO: [OCL_UTIL] log: /home/palazza/Vitis_Libraries/hpc/L2/tests/rtm2d/rtm/build_dir.hw.xilinx_u280_xdma_201920_3/link/vivado/vpl/prj/prj.runs/impl_1/runme.log
ERROR: caught error: problem implementing dynamic region, impl_1: opt_design ERROR, please look at the run log file '/home/palazza/Vitis_Libraries/hpc/L2/tests/rtm2d/rtm/build_dir.hw.xilinx_u280_xdma_201920_3/link/vivado/vpl/prj/prj.runs/impl_1/runme.log' for more information
[14:43:25] Run vpl: Step impl: Failed
INFO: [OCL_UTIL] current step: vpl.impl failed. To rerun the existing project please use --from_step vpl.impl
problem implementing dynamic region, impl_1: opt_design ERROR, please look at the run log file '/home/palazza/Vitis_Libraries/hpc/L2/tests/rtm2d/rtm/build_dir.hw.xilinx_u280_xdma_201920_3/link/vivado/vpl/prj/prj.runs/impl_1/runme.log' for more information
INFO: [Common 17-206] Exiting Vivado at Tue Dec 15 14:43:25 2020...

In order to help the debug, I attach some reports taken from the build directory[
VitisError.zip
](url)

Cannot build Sparse example (for Alveo U50 - for 16 Compute Units) in Vitis GUI

Hello. I want to ask something about the SPARSE library. You have 2 demos in L2/tests directory, cscmv and cscmvSingleHbm. The first targets U50 and U280 platforms, whereas the second U280 only.
The second one can be used as a template for testing in Vitis GUI, while the first one cannot.

I managed to build the cscmv example from terminal and run it on an Alveo U50 without a problem. However, I want to do everything through Vitis, so that I can utilize run_summary and other capabilities that Vitis GUI offers.

I made some modifications and created a copy of cscmvSingleHbm folder (named cscmv_test - you can find it here), and modified description.json so that it will be visible in Vitis, and several other modifications so that it can use 16 Compute Units and be equivalent to the cscmv example (I also copied Makefile, utils.mk and {*}.cfg from cscmv folder)

However, when I try to build sw_emu version, it fails during linking, with the fail message being
ERROR: [v++ 17-1309] Gcc: /opt/xilinx/Vitis/2020.2/bin/../data/emulation/include/xcl_top_defines.h:9:‘packetType {aka struct ap_uint<128>}’ has no member named ‘data’

In addition, after trying to build hw_emu version, the fail message now is :
ERROR: [CFGEN 83-2284] No stream resources found that can accomodate compute unit "loadColKernel_0.out0"

Sorry if this is not the right place to ask this question, but can you wonder what I am doing wrong ?

Instructions should use setup.sh and not setenv.sh for XRT setup

L2 instructions use:

source < path-to-XRT-installation-directory >/setenv.sh

But it should be:

source < path-to-XRT-installation-directory >/setup.sh

McEuropeanHestonGreeksEngine data transfer issue

When trying to run an L2 test of McEuropeanHestonGreeksEngine I get zeros for all except the first value:

$ make run TARGET=sw_emu DEVICE=u200
export XCL_EMULATION_MODE=sw_emu; \
/home/common/ven_veremin/SDx/Vitis_Libraries-master/quantitative_finance/L2/tests/MCEuropeanHestonGreeksEngine/bin_xilinx_u200_xdma_201830_2/host.exe -xclbin /home/common/ven_veremin/SDx/Vitis_Libraries-master/quantitative_finance/L2/tests/MCEuropeanHestonGreeksEngine/xclbin_xilinx_u200_xdma_201830_2_sw_emu/MCEHGEngine_k0.xclbin
----------------------McEuropeanHestonGreeksEngine-----------------
Found Platform
Platform Name: Xilinx
Found Device=xilinx_u200_xdma_201830_2
INFO: Importing /home/common/ven_veremin/SDx/Vitis_Libraries-master/quantitative_finance/L2/tests/MCEuropeanHestonGreeksEngine/xclbin_xilinx_u200_xdma_201830_2_sw_emu/MCEHGEngine_k0.xclbin
Loading: '/home/common/ven_veremin/SDx/Vitis_Libraries-master/quantitative_finance/L2/tests/MCEuropeanHestonGreeksEngine/xclbin_xilinx_u200_xdma_201830_2_sw_emu/MCEHGEngine_k0.xclbin'
kernel has been created
kernel start------
kernel end------
Execution time 122036782us
difference :
    0: 0.000757404
    1: 0.10813
    2: 0.506724
    3: 1.0021
    4: 4.34831e-06
    5: 0.406697
    6: 3.47461e-06
    7: 0.00260451
theta: -0.0483559, rho: 0, delta: 0, gamma: 0, MV_kappa: 0, MV_theta: 0, MV_KHI: 0, MV_VO: 0

If values are printed directly from the kernel in sw_emu they are correct:

Kernel results:
-0.048356
-0.108764
0.508515
1.005469
-0.000003
0.407388
0.000424

So the issue is obviously with data transfer from kernel to host.

CMake set(CMAKE_CXX_COMPILER /path_to/v++) compiler support

Hello,

I have added a bunch of the PyTorch kernels here for Vitis. I was able to get things working using system calls from CMake, but I would appreciate if Vitis would support:

The ability to specify v++ as a c++ compiler using set(CMAKE_CXX_COMPILER /path_to/v++).
The ability to find_package(Vitis) within CMake instead of running .sh commands to configure the environment.

This implicitly needs to be located inside the Xilinx Vitis installation and not Vitis Libraries or Vitis AI
Related:

Vitis AI cmake folder

CMake toolchain docs

CMake find_package docs.

vitis vision opencv version?

I am having issues in compiling the vision examples on a CentOS 7-based machine with Vitis 2020.1 by using the Makefile provided.

I do get as error what follows

xf_warp_transform_tb.cpp:104: undefined reference to `cv::imread(std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&, int)'
xf_warp_transform_tb.cpp:121: undefined reference to `cv::imwrite(std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&, cv::_InputArray const&, std::vector<int, std::allocator<int> > const&)'
xf_warp_transform_tb.cpp:121: undefined reference to `cv::imwrite(std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&, cv::_InputArray const&, std::vector<int, std::allocator<int> > const&)'

I am trying with OpenCV4.4 module.
Is this an issue related to my OpenCV version, or is it something else?

Thank you in advance

How to use database library

Hi.
The vitis database library L3 is currently being compiled successfully.
After that, I'm thinking of connecting the vitis database library with PostgreSQL to offload SQL processing to the FPGA.
However, it seems that the mechanism is not provided.
I checked your company's github at this URL and it seems that "xpgbolt.so" is the mechanism that connects postgreSQL and FPGA.
Can this library be used with the vitis database library?

L2/Gzip/demos compression and decompression validation failed

I use my own test data, and data size is 512MB to test compression and decompression functions in L2/Gzip/demos but validation failed. the size of data.gz.orig is obviously smaller than original size. Is there any limit on the size of the test data ? (Implement Platform is u200)

Issue with security library

Used security library I am trying to get the following benchmark results replication on the U250 card.

https://xilinx.github.io/Vitis_Libraries/security/2020.2/benchmark/result.html#aes256cbcencrypt-throughput

While performing HW build for AES cbc encryption on Vitis IDE, I got logs as follows:

hw.log

But I am able to perform HW build for AES cbc decryption on Vitis IDE successfully.

compoundSort Benchmark unable to support 2M keys

File:

https://github.com/Xilinx/Vitis_Libraries/blob/master/database/L1/benchmarks/compound_sort/kernel/kernel_sort.hpp

kernel_sort.hpp line 28:

#define LEN (INSERT_LEN * 4 * 32) // max length support: 1024*4*512

If I change it to:

#define LEN (INSERT_LEN * 4 * 512)

where INSERT_LEN remains 1024

in order to support 2M keys (power of 2), it gets stuck at:

INFO: [v++ 60-242] Creating kernel: 'SortKernel'

the only way I get a working bitstream is if I keep line 28 as is.

I am using Vitis 2020.2 with XRT up to date. U280 card on CentOS 7.6.1810 server

where can I find the standalone hls example using Vitis_libraries vt::cv?

xfopencv was superseded by vitis_libraries. However, I cannot find any examples on how to use vitis libraries
in standalone HLS application.

Below is for using xfopencv
https://github.com/Xilinx/xfopencv/tree/master/HLS_Use_Model/Standalone_HLS_Example

How about for using vt::cv?

Quantitative Finance SVD -support for newer shells

Only older shell version currently supported (201830_1?)

Vitis_Libraries/quantitative_finance/L1/benchmarks/SVD/Makefile

Line 230 in 40b98f7

# U200 and U250

Adding switch in makefile for 2019 shell with -sp DDR[0] (instead of "bank0") would allow design to be run with more recent shell(s)

E.g. This works for U250 xilinx_u250_qdma_201920_1 (but not tested with other 2019 shells; different awk pattern match may be needed):

else ifneq (,$(shell echo $(XPLATFORM) | awk '/u2[50]0/*/2019/'))
VPP_CFLAGS += --sp $(KERNEL)_0.m_axi_gmem0:DDR[0]
VPP_CFLAGS += --sp $(KERNEL)_0.m_axi_gmem1:DDR[0]
VPP_CFLAGS += --sp $(KERNEL)_0.m_axi_gmem2:DDR[0]
VPP_CFLAGS += --sp $(KERNEL)_0.m_axi_gmem3:DDR[0]

How to change the value of VBNV?

Hi,

I am testing a database library using two FPGA cards.
Specifically, it is the following test.

root@Vitis-Test:/insight/xilinx/Vitis_Libraries/database/L3/tests/gqe/aggregate/build_dir.hw.xilinx_u280_xdma_201920_3# ./test_q1.exe -xclbin /insight/xilinx/Vitis_Libraries/database/L3/build/vt_database_aggr-xilinx_u280_xdma_201920_3.xclbin
--------------- Query 1, aggregation ---------------
dat dir is: db_data//dat1
file exist, skip generate.
file exist, skip generate.
file exist, skip generate.
file exist, skip generate.
file exist, skip generate.
file exist, skip generate.
file exist, skip generate.
Read Input table form db_data//dat1
Using StrategyManualSet
Select solution:2
Lineitem SF(1)  6001215 rows
Result table    1000 rows
LineItem table has been read from disk
INFO: selected device 0: xilinx_u280-es1_xdma_201910_1
INFO: initilized context.
INFO: initilized command queue.
XRT build version: 2.8.743
Build hash: 77d5484b5c4daa691a7f78235053fb036829b1e9
Build date: 2020-11-16 00:19:11
Git branch: 2020.2
PID: 114286
UID: 0
[Mon Mar  1 13:15:36 2021 GMT]
HOST: Vitis-Test
EXE: /insight/xilinx/Vitis_Libraries/database/L3/tests/gqe/aggregate/build_dir.hw.xilinx_u280_xdma_201920_3/test_q1.exe
[XRT] ERROR: Xclbin does not match shell on card.
[XRT] ERROR: Shell VBNV is 'xilinx_u280-es1_xdma_201910_1'
[XRT] ERROR: Xclbin VBNV is 'xilinx_u280_xdma_201920_3'
[XRT] ERROR: Use 'xbmgmt flash' to update shell.
[XRT] ERROR: See dmesg log for details. err=-95
[XRT] ERROR: Failed to load xclbin.
ERROR: fail to program PL

As you can see, the shell being called is different and the test cannot be executed.
Could you please tell me how to change the value of VBNV?

L1/examples/SGBM hls转换后资源过大，且和api-reference差距较大问题

使用vitis_hls 2020.2对sgbm进行rtl转换，结果和api-reference.rst中给出的参考资源差别很大。
使用的tcl脚本：
https://github.com/Xilinx/Vitis_Libraries/blob/master/vision/L1/examples/sgbm/run_hls.tcl
同时参考api-reference.rst中，将xf_config_params.h修改成如下：

        #define HEIGHT 1080//720
        #define WIDTH 1920//1280
        
        /* set penalties for SGM */
        #define SMALL_PENALTY 20
        #define LARGE_PENALTY 40
        
        /* Census transform window size */
        #define WINDOW_SIZE 5
        
        /* NO_OF_DISPARITIES must be greater than '0' and less than the image width */
        #define TOTAL_DISPARITY 64
        
        /* NO_OF_DISPARITIES must not be lesser than PARALLEL_UNITS and NO_OF_DISPARITIES/PARALLEL_UNITS must be a
         * non-fractional number */
        #define PARALLEL_UNITS 32
        
        /* Number of directions */
        #define NUM_DIR 4

hls输出的报告如下：

        + Timing: 
            * Summary: 
            +--------+---------+----------+------------+
            |  Clock |  Target | Estimated| Uncertainty|
            +--------+---------+----------+------------+
            |ap_clk  |  3.30 ns|  8.010 ns|     0.89 ns|
            +--------+---------+----------+------------+
        
        + Latency: 
            * Summary: 
            +---------+---------+-----------+-----------+---------+---------+----------+
            |  Latency (cycles) |   Latency (absolute)  |      Interval     | Pipeline |
            |   min   |   max   |    min    |    max    |   min   |   max   |   Type   |
            +---------+---------+-----------+-----------+---------+---------+----------+
            |  2088739|  8668900|  16.731 ms|  69.438 ms|  2088724|  8668880|  dataflow|
            +---------+---------+-----------+-----------+---------+---------+----------+
        
        ================================================================
        == Utilization Estimates
        ================================================================
        * Summary: 
        +-----------------+---------+------+--------+--------+-----+
        |       Name      | BRAM_18K|  DSP |   FF   |   LUT  | URAM|
        +-----------------+---------+------+--------+--------+-----+
        |DSP              |        -|     -|       -|       -|    -|
        |Expression       |        -|     -|       0|      28|    -|
        |FIFO             |        -|     -|    1782|    1206|    -|
        |Instance         |      211|   134|   31051|   68952|    -|
        |Memory           |        -|     -|       -|       -|    -|
        |Multiplexer      |        -|     -|       -|      45|    -|
        |Register         |        -|     -|       5|       -|    -|
        +-----------------+---------+------+--------+--------+-----+
        |Total            |      211|   134|   32838|   70231|    0|
        +-----------------+---------+------+--------+--------+-----+
        |Available        |     1824|  2520|  548160|  274080|    0|
        +-----------------+---------+------+--------+--------+-----+
        |Utilization (%)  |       11|     5|       5|      25|    0|
        +-----------------+---------+------+--------+--------+-----+

api-reference.rst 中给出的latency和资源报告如下：

           +                +               +------------------+-----------+-------+-------+

| | | | BRAM_18K | DSP_48Es | FF | LUT |
+================+================+===========================+==================+===========+=======+=======+
| 1 Pixel | 5x5 | 200 | 205 | 141 | 11856 | 19102 |
+----------------+----------------+---------------------------+------------------+-----------+-------+-------+
.. rubric:: Performance Estimate
The following table summarizes a performance estimate for a 1920x1080
image.
.. table:: Table . SemiGlobalBM Function Performance Estimate Summary
+-------------+-------------+-------------+-------------+-------------+
| Operating | Operating | Number of | Parallel | Latency |
| Mode | Frequency | Disparities | Units | |
+=============+=============+=============+=============+=============+
| 1 | 200 MHz | 64 | 32 | 42 ms |
| pixel/clock | | | | |
+-------------+-------------+-------------+-------------+-------------+

可以看到，api-reference中给出的LUTs只有19k，而我这里转换出的LUTs有70k，请问问题在哪里？如何进行优化，降低资源？
能否提供转换后得到19k luts资源的脚本和对应的详细配置
谢谢

Vitis Software Platform for Trial

Hi,

Is there a way to get trail version of the software?
I would like to simulate the library, to develop expertise in High Level Synthesis using Vitis.

Thanks & Regards,
Bhavna

Gzip decompression error with Alveo U50

Hi,

We have tried to use Gzip decompression/compression with Alveo U50.
Here are the errors when use the default test and our customized test data.

Hardware platform: Alveo U50
OS: Ubuntu 18.04
XRT: xrt_202010.2.7.766_18.04-amd64-xrt.deb

make run TARGET=hw DEVICE=u50
Error message as below.

We use the test data as the below website.
http://sun.aei.polsl.pl/~sdeor/index.php?page=silesi
The compression of all data are good but there are errors when decompression.
Error message as below.

U250 support query

https://github.com/Xilinx/Vitis_Libraries/tree/master/database/L1/tests/hw/bitonic_sort

Does alveo U250 support HW run for the above example?

Xilinx Tree Swaption Engine HW Model Benchmark testing

I tried to test the following benchmark template from the Vitis Quantitative Finance libraries.
Xilinx Tree Swaption Engine HW Model Benchmark (see attached screenshot)

When running the SW build I have the following errors (screenshot attached)

Could you please advise how the project should be created/configured to manage the dependencies?

Relation of "ZIP BOMB" information and maximum compression ratio as fpga::gzip decompress

I use std::gzip to compress data and then use fpga::gzip to decompress, but it throw out this information. It shows below :

root@Chromium sw_gzip $ xil_gzip -sx /opt/xgzip/compress_decompress.xclbin -d spark3_new.dump.gz
Found Platform
Platform Name: Xilinx
Using Device: xilinx_u200_xdma_201830_2
INFO: Reading /opt/xgzip/compress_decompress.xclbin
Loading: '/opt/xgzip/compress_decompress.xclbin'
KT(MBps)                :

ZIP BOMB: Exceeded output buffer size during decompression

Use -mcr option to increase the maximum compression ratio (Default: 10)

Aborting ....

Segmentation fault (core dumped)

And then I check default value of -mcr , the default value is 20.

root@Chromium sw_gzip $ xil_gzip --help

===========================================================
Usage: application.exe, -[-h-c-d-sx-v-dev-l-k-mcr]

          --help,                    -h       Print Help Options         Default: [false]
          --compress,                -c       Compress
          --decompress,              -d       DeCompress
          --single_xclbin,           -sx      Single XCLBIN
          --compress_decompress,     -v       Compress Decompress
          --device,                  -dev     FPGA Card # to be used
          --file_list,               -l       List of Input Files
          --cu,                      -k       CU                         Default: [0]
          --max_cr,                  -mcr     Maximum CR                 Default: [20]

But when I set -mcr 10, fpga::gzip can decompress successfully.
Is this situation reasonable ?
And how can I use -mcr ?

Building the cornertracker example on xilinx_u200_xdma_201830_2 fails

I tried building the cornertracker example on xilinx_u200_xdma_201830_2 and got a link error:

INFO: [VPL 60-1032] Extracting hardware platform to /home/tbollaer/Work/Labs/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_xilinx_u200_xdma_201830_2_hw/link/vivado/vpl/.local/hw_platform
[20:30:11] Run vpl: Step create_project: Started
Creating Vivado project.
[20:30:16] Run vpl: Step create_project: Completed
[20:30:16] Run vpl: Step create_bd: Started
[20:31:47] Run vpl: Step create_bd: RUNNING...
[20:32:21] Run vpl: Step create_bd: Failed
[20:32:26] Run vpl: FINISHED. Run Status: create_bd ERROR

===>The following messages were generated while creating FPGA bitstream. Log file: /home/tbollaer/Work/Labs/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_xilinx_u200_xdma_201830_2_hw/link/vivado/vpl/vpl.vdi :
ERROR: [VPL-1] /cornerTracker_1/m_axi_gmem1 is associated to /cornerTracker_1/ap_clk on /cornerTracker_1 but this clock pin is not connected to a clock source...
ERROR: [VPL 60-773] In '/home/tbollaer/Work/Labs/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_xilinx_u200_xdma_201830_2_hw/link/vivado/vpl/runme.log', caught Tcl error: ERROR: [Common 17-39] 'send_msg_id' failed due to earlier errors.
ERROR: [VPL 60-773] In '/home/tbollaer/Work/Labs/Vitis_Libraries/vision/L3/examples/cornertracker/build/_x_xilinx_u200_xdma_201830_2_hw/link/vivado/vpl/vivado.log', caught Tcl error: ERROR: [Common 17-39] 'send_msg_id' failed due to earlier errors.
ERROR: [VPL 60-704] Integration error, Failed to update block diagram in project required for hardware synthesis.The project is 'prj'. The block diagram update script is '.local/dr.bd.tcl'. The block diagram update script was generated by system linker. An error stack with function names and arguments may be available in the 'vivado.log'.
ERROR: [VPL 60-1328] Vpl run 'vpl' failed
ERROR: [VPL 60-806] Failed to finish platform linker
INFO: [v++ 60-1442] [20:32:30] Run run_link: Step vpl: Failed
Time (s): cpu = 00:00:18 ; elapsed = 00:03:23 . Memory (MB): peak = 686.980 ; gain = 0.000 ; free physical = 2333 ; free virtual = 93413
ERROR: [v++ 60-661] v++ link run 'run_link' failed
ERROR: [v++ 60-626] Kernel link failed to complete
ERROR: [v++ 60-703] Failed to finish linking

I believe this is coming from the --clock.defaultFreqHz ${VIVADO_FREQUENCY} constraint on line 215 of the Makefile:
https://github.com/Xilinx/Vitis_Libraries/blob/master/vision/L3/examples/cornertracker/build/Makefile#L215

I took this out and the run proceeded past the previous point of failure (but isn't finished yet).

How to use REVERSE FFT?

When I use REVERSE FFT on zcu102,System crash. But use FORWARD FFT ,it success , why? This is the code

#include "vt_fft.hpp"
#define FFT_LEN 4096
#define SSR 4
#define IN_WL 18
#define IN_IL 14
#define TW_WL 18
#define TW_IL 14
#define IID 0

using namespace xf::dsp::fft;
typedef std::complex<ap_fixed<IN_WL, IN_IL> > T_in;

// Define parameter structure for FFT
struct fftParams : ssr_fft_default_params {
static const int N = FFT_LEN;
static const int R = SSR;
static const scaling_mode_enum scaling_mode = SSR_FFT_NO_SCALING;
static const fft_output_order_enum output_data_order = SSR_FFT_NATURAL;
static const int twiddle_table_word_length = TW_WL;
static const int twiddle_table_intger_part_length = TW_IL;
//static const transform_direction_enum transform_direction = FORWARD_TRANSFORM;
static const transform_direction_enum transform_direction = REVERSE_TRANSFORM;
};
typedef ssr_fft_output_type<fftParams, T_in>::t_ssr_fft_out T_out;

T_in p_inData[SSR][FFT_LEN / SSR];
T_out p_outData[SSR][FFT_LEN / SSR];
for (int r = 0; r < SSR; ++r)
{
for (int t = 0; t < FFT_LEN / SSR; ++t) {
p_inData[r][t] = std::complex<ap_fixed<IN_WL, IN_IL> >(4,4);
}
}

fft(p_inData,p_outData);

Issues with sd_card generation for embedded Vitis_Libraries/vision/L2/ examples

From these instructions: https://github.com/Xilinx/Vitis_Libraries/tree/master/vision/L2#commands-to-run

For an edge device creation of sd_card is not as simple as:

make run TARGET=< sw_emu|hw_emu|hw > BOARD=Zynq ARCH=< aarch32 | aarch64 >

As of 2020.1 the following will creep up:

Makefile 'run' target is now using SYSROOT for more than just the sysroot location. Consequently, it's not enough to just point to a sysroot location. The provided path has to meet specific requirements. In particular, it expects the sysroot to be located as a child directory of an extracted "Common images for Embedded Vitis platforms" archive (which isn't the default SDK location). For example, in the case of ZynqMP the sysroot must have the path .../xilinx-zynqmp-common-v2020.1/sysroots/aarch64-xilinx-linux
Makefile 'run' target also expects an uncompressed version of the rootfs, but the archive of common components provides a compressed version. So, for example, the file .../xilinx-zynqmp-common-v2020.1/rootfs.ext4.gz must be extracted at it's current location for the 'run' target to succeed.

Probably best to update the Makefile such that these requirements aren't necessary. For example, use separate env-vars for location of sysroot and location of common-archive contents such that there is no "../.." dependency. And ideally the Makefile would work with the supplied rootfs.ext4.gz otherwise additional instructions are needed.

Instructions should also explicitly state the need for the archive from "Common images for Embedded Vitis platforms".

SSR FFT creates ap_memory instead of ap_fifo

Hi, I synthesized 1D SSR FFT and according to the documentation I should get ap_fifo interface but I'm getting ap_memory.
FFT length is 1024 and SSR factor is 8.
Here is the link to Xilinx forum for more detailed explanation.

I'm using Vitis 2020.1. HLS 2019.1 produced correct ap_fifo interface.

Alveo U200 & U250 - Data center FPGA board platforms

Hi,

For Xilinx Edge device, board platform source given here - https://github.com/Xilinx/Vitis_Embedded_Platform_Source

From where I can get board platforms for Data center cards - Alveo U200 & U250?