kapil2099 Goto Github PK

advanced-cplusplus

automl

Google Brain AutoML

coursera-ml-andrewng-notes

吴恩达老师的机器学习课程个人笔记

coursera_c2c-

cousera course

coursera_c2cpp

Homework code of C++ For C Programmers on Coursera. The course website is https://class.coursera.org/cplusplus4c-002/class/index

design-and-verification-of-ddr3-memory-controller

The memory model was leveraged from micron.

git-jokes

Collection of questionably humorous git sayings

hardh264

A hardware h264 video encoder written in VHDL. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools and FPGAs but it is not specific to Xilinx.

hash-function-benchmark

Benchmark of common hash functions

huaweicloud-fpga

The official repository of the HUAWEI CLOUD FPGA Development Kit based on HUAWEI CLOUD FPGA Accelerated Cloud Server.

matrix-multiplication-threading

Matrix multiplication using c++11 threads

neuralnetworkbasedbranchpredictor

Branch prediction using simple perceptron and path based perceptron

numactl

NUMA support for Linux

opencl-based-hardware-acceleration

Demonstrated acceleration achieved due to parallel computing on FPGA is much higher than that achieved on a Multicore CPU. Matrix Multiplication of two 1000x1000 matrices (A and B) was used for demonstration. This includes computation of 1 million data points. A Kernel was developed that would work on one row of Matrix and one column of matrix B at a time. OpenCL allows to replicate these kernels, generating parallel design blocks on the FPGA. Buffers were created on the FPGA which will hold the data of the two matrices. Each Kernel will read from a specific location, perform its operation and store the result in another buffer eventually to form Matrix C which is the resultant matrix. Use of OpenCL added an abstraction layer which would convert the code written in C to a netlist further to form a bitstream to be synthesized on the FPGA.

vitis_accel_examples

Vitis_Accel_Examples

vitis_libraries

Vitis Libraries

xrt

Xilinx Run Time for FPGA