Question about Vitis SPARSE library about vitis_libraries HOT 4 CLOSED

Hi, your understanding is right. The idea is to put readWriteHbm kernel close to the HBM banks, which reside in SLR0. However, there is not enough resource in SLR0 to put readWriteHbm kernel and cscRowKernel. Hence, in the configuration file, the second readWriteHbm kernel is positioned in SLR1. This design just demostrate the flexibility with configuring kernel's location when you use kernel-to-kernel streaming design.

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Ok, thank you for the really quick answer!
I will test this, but just asking, in case you already tested it. Could you place all cscRow CUs in SLR1 and both readWriteHbm CUs in SLR0? Or this would be suboptimal from performance perspective, even if there are enough resources to support such a design?

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I think I tried this. That would be suboptimal in terms of achievable clock frequncy. The reason might be when you place readWriteHBM in SLR1, you can leverage dedicated SLR cross for HBM controllers.

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Ok, makes sense. Thank you very much!

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