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View Code? Open in Web Editor NEWA DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
I'm not really sure if this is an issue with the code or with Vivado itself. I'm not that experienced with Vivado.
I created a new project in Vivado 2020.2 and added your source files. I added the FIFO generator from the IP Catalog.
However, I still see this
I'm not sure what it represents or how to get rid of it. Has anyone else encountered this?
“localparam lpdiv_CCD = lp_BL/2/2 - 1; // WRITE-to-WRITE (actually just BL/2 in DDR CK)(CCD = CAS#-to-CAS# delay)”Why here minus one?
I noticed ODT is pulled low and not used. Why is it so and would not having it cause failures when operating in rare conditions ?
Hello, I am very interested in this project, and I have met some problems in my study.
I have instantiated the ddr3_x16_phy_cust
and ddr3_rdcal
modules in your Arty S7-50 project, and programmed the app module to generate the rdcal_start
signal and control the data and address input of the ddr3_rdcal
module.
The parameters as a whole follow your configuration.
The DDR interface frequency is 300M, ISERDES_16B, 32B, and 48B are both FALSE. The IDELAYCTRL frequency is 200M. The RD_DELAY is set to 6/10(Same phenomenon), and is deployed on zynq7030.
The board level tests are as follows:
After the w_rdcal_done
signal is high, the single read/write test passes. Data written and read at address 0x10 are both 0xaaaa_aaaa_aaaa_aaaa. For details, see the following figure :
However, the problem occurs when the data is read after continuous writing. At address 0x0, full A is written to address 0x8, and full B is written to address 0x10. The data read at address 0x0 is full C, and the full A is different. For details, see the following figure :
According to the waveform, when the write operation is effective, the write data will be updated to the read data repository. In this way, the data read for the first time is the data written for the last time, which has nothing to do with the address.
I haven't studied your code in depth, so I want to study it further after running it through first. What is the problem according to your experience?
Looking forward to your reply and guidance, thank you!
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