ODT Support ? about ddr3-controller HOT 3 CLOSED

Thank you for your interest in my work.

Some documentation (e.g. Micron) often mixes up ODT and dynamic ODT, but there is a clear distinction between the two features.

In this interface, ODT impedances are set via the mode registers. See localparam lp_MR1. See the JEDEC spec or your part datasheet for possible options, the value I've chosen here corresponds to RZQ/6 (40 Ohm) for both writes and non-writes. This should be in line with Digilent's recommendation for MIG configuration on an Arty S7-50, which is also the only board I personally had the opportunity to run tests on.

Dynamic ODT is disabled in this interface via MR2, and the ODT ball is pulled low, as you've noted. Dynamic ODT is an optional feature in DDR3 SDRAM. It enables the data bus lines to have their impedance changed on the fly (effectively switching between the values set in MR1 and MR2), but doing this is not necessary if the data bus is used by a single memory chip. Intel explains it nicely:

In the multi-load DDR3 SDRAM configuration, dynamic ODT helps reduce the jitter at the module being accessed, and minimizes reflections from any secondary modules.

Adding support for multi-chip arrangements that share a data bus should be trivial, but I doubt many FPGA projects would implement SDRAM like this. If larger memory capacity is required, it should be simpler to simply purchase a multi-die memory chip (available in 8 Gb, e.g. Micron's TwinDie MT41K512M16), rather than try and fit two memory chips onto the PCB.

See also JEDEC JESD79-3F chapter 5: On-Die Termination (ODT).

If you wish to discuss anything privately, feel free to contact me.

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Woah thanks for all that information! Super helpful, i'll be sure to contact you.

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how do i contact you lol ? Would discord be a good avenue ? Animatrix#0191

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