Hi!
So here is a single core BP Verilog file generated by bsg_sv2v. I'm trying to run it through the flow, but I'm getting strange Yosys errors. Any ideas on were the problem might be?
The error is: input buffer overflow, can't enlarge buffer because scanner uses REJECT ERROR: Fail Yosys for benchmark bp.
bp_top.v.txt

Is your feature request related to a problem? Please describe.
I would like to know the commit used to build the current binary of openfpga-shell.
Especially important when only binary is distributed without source.

Describe the solution you'd like
I would like to see the commit SHA on when openfpga-shell is launched

Describe alternatives you've considered
I guess above solution is plausible. It has been implemented in the VPR tool, so the same idea can be implemented here.

Additional context
Here is the launch message VPR command prints in shell.

OpenFPGA> vpr
                      VPR FPGA Placement and Routing.
                      Version: 0.0.0+5f613c4
                      Revision: 5f613c4
                      Compiled: 2021-01-20T19:41:55
                      Compiler: GNU 8.4.0 on Linux-5.4.0-1032-azure x86_64
                      Build Info: Release VTR_ASSERT_LEVEL=2

Note : You might need to handle a case when binary is build using ZIP download source code instead of cloned repository. In that case we can keep the SHA field empty.

In FPGA SPice, when using the --print_top_testbench option, it creates a top testbench netlist which instantiates all the other components (SB, CB, CLBs, etc.) as well as the testbench components (measure commands, voltage sources, etc) in a single file.I would be cleaner to create two file:1- the top spice netlist of the FPGA, which simply instantiates all the other components (SB, CB, CLBs, etc.)2- the top spice tesbench netlist, which instantiate the top FPGA and the other testbench components.

I noticed multiple issues in the current task run flow. It looks to have various hard-codings or assumptions.
My intention is to write a testcase to run yosys by invoking synth_quicklogic and here are the issues/challenges I faced:

1. File to run a task - task.conf expects only these 4 synthesis parameters:

• Top_module
• Chan_width
• Act
• Verilog

2. The issue with above approach is that it expects yosys to run only with these variables. I gone through run_fpga_flow.py script:

• Looks like this script has a hardcoded yosys template file name - ys_tmpl_yosys_vpr_flow.ys
• It just picks the above 4 variables and put it in this file. Then this file is used for yosys run.

3. I think the current approach may not run for yosys cmdline options like: synth_quicklogic. Similar cmdline options are there for other devices also in yosys. I think we need to update this script to support this kind of variables.

4. Moreover, with task.conf approach, I was not even able to run yosys. So, I ran the script in the following manner:

• python3 ${OPENFPGA_PATH}/openfpga_flow/scripts/run_fpga_flow.py ${OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_40nm.xml ${OPENFPGA_PATH}//openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml --top_module counter --run_dir tmp --yosys_tmp counter.ys

5. Please note that in the above commandline, even if I provided option “—yosys_tmp” but the script does not use this option at all to take the template file as input, rather it always picks “ys_tmpl_yosys_vpr_flow.ys”

Hello,
Can you provide me an email address? So we can schedule a conference call? Thanks

Originally posted by @tangxifan in #48 (comment)

Hi, my e-mail is [email protected].
My English is poor, so our conversation may be more appropriate by writing the words. Thank you!

The chans are useful for debugging and following where the signals go but it creates another level of hierarchy for the PNR which creates congestion because it funnels all the signals through a small block without any silicon.

TODO: Option to merge the cbs and the chans. The chan modules would disappear and be directly incorporated into the cbs. This way we would only have physical blocks throughout the design

Screenshot of ICC2 showing that it cannot do its job:

Inside of the source code, we use generation functions which allocate the memory dynamically and create strings which we output. Usually, we use these functions inside of the fprintf because it is faster and kinda cleaner. The issue is that the memory is impossible to free later down the road because of not having a variable which we can free.

This is a known issue and will work on it when more time is on my hands.

Hello,
im now working on the bitstream generation for the new custom block, for example blackbox.
According to your paper TGA+19, i generate a physical mode and an operating mode, both have the module adder(because there's only one module: adder in the blackbox). Afterwards i combine them in the openfpga-arc.
But the issue is that the bitstream isn't changed. It still only has "clb" block and "swich" block, what means the bitstream for blackbox isn't generated.
can you please give me some advice about that?
k4_N4_.zip

Hello,

sorry for the disturb again. I kinda have a new problem.
I made a few changes in the k6_frac_N10_adder_chain_40nm_openfpga.xml. For example, i wrote a 8-to-1 multiplexer and used it in the connection box. In addition i changed the configuration protocol with a new customized D-Flipflop.
After i ran it manually, i got the response: Assertion "true == model_is_default(default_id)" is failed

Would you give me any advice?

Is your feature request related to a problem? Please describe.
As OpenFPGA now uses Github Action for continuous integration, the travis settings should be removed.

Describe the solution you'd like
Remove the travis run settings and scripts under the directory

We need to make sure the content of the .route file is consistent with the routing while the tillable option is activated.

Probably non-critical...

Built from main. In Ubuntu 18.04 cmake gives the following error on missing X11. the regular dependancy installation attempts all failed to make a difference.

-- Could NOT find X11 (missing: X11)
CMake Warning at vpr7_x2p/vpr/CMakeLists.txt:23 (message):
Failed to find required X11 library (on debian/ubuntu try 'sudo apt-get
install libx11-dev' to install)
-- Add flags to disable graphics in VPR compilation: -DNO_GRAPHICS

Not sure if this will be an issue downstream when running vpr?

A Makefile is produced and at first glance the build process seems ok...

Can you add a example/command sequence for how to test if install works in the README?

Describe the bug
OpenFPGA has embraced the shell-like interface while the old command-line interface has been dropped, as said in #136
In addition to the dead code, the documentation is out-of-date as well.
This is also valid for new features undergoing #134

Expected behavior
The documentation has to be reworked about the OpenFPGA task-run scripts, including both run_fpga_task.py and run_fpga_flow.py

In wires.v, you define a module:

module direct_interc (
input wire in, output wire out);
assign out = in;
endmodule

This module is later on instanciated the for the CLB and the top (IO blocks):

direct_interc direct_interc_0_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ );

That would be better to replace this module instantiation by the assign command directly.
That way, when uniquifying the design during the P&R, this will greatly reduce the number of "duplicated" module instantiations and makes the flow run faster, especially for large FPGAs.

Hi, I tried to run openfpga shell by using run_fpga_task.py. When the flow I chose was vpr_blif, the result was successful, but the flow I chose was yosys_vpr, the result was error. This is report about the reason of the error.

00_FSM_top_MIN_ROUTE_CHAN_WIDTH_out.log

My solution was using yosys_vpr flow to runing the section of yosys first, then generating benchmark.blif, benchmark_ace_out.act, benchmark_output_verilog.v. Finally, using those three files to run vpr_blif flow. This can be a temporary way to run a complete flow of openfpga shell.

Describe the bug
Hi Ganesh/XiFan:

Just want to give you an update on the verification that Rakesh is running and we notice of the following to see if this can be taken care of in OpenFPGA:

a) It looks like the IO_ISOL_N polarity is inverted.
Looks like the polarity of “IO_ISOL_N” is incorrectly set in the test bench.
The assignment shows that IO_ISOL_N is the inversion of config_done. That essential will put “IO_ISOL_N” to “0”, which will tristate the IO in the normal mode.

The following simulation shows that if line 141 is used, the output is tristated.The following simulation shows that if line 141 is used, the output is tristated.

b) All SOC_OUT have an assignment to 1’b0;
I understand where this is coming from where Caravel probably requested for tristating the IO during configuration. At the eFPGA level, by assigning the 1’b0 to any unused IO could hide some issue that we may not be observable. For example, if the SOC_OUT is not tristated as intended and it is driving a “0”, we may not know until later that there was an issue.

Do you guys agree?

Hi,
i got a new problem.
After i use commend "python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/full_testbench/configuration_chain" to generate the verilog code, i find the module in the file "user_defined_templates.v" is not defined (Screenshot 1), although it was already described in the architecture xml.file. (Screenshot 2).

Hello, i try to generate the Verilog netlists and testbenches with the command "python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/configuration_chain" you have given on the toturial.
But the application is crash because of a memory-access-error (core dumped) --> abgebrochen(Speicherabzug abgeschrieben)

To Reproduce
Steps to reproduce the behavior:
1]Make a directory in scripts folder called "test"
2] ~/Desktop/OpenFPGA/openfpga_flow/scripts/test$ python3 ../run_fpga_flow.py
../../openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml
../../benchmarks/micro_benchmark/and2/and2.blif --top_module and2.v

Screenshots

Enviornment (please complete the following information):
anesh@ganesh:istributor ID: Linuxmint
Description: Linux Mint 20
Release: 20
Codename: ulyana
gcc_version: gcc (Ubuntu 9.3.0-17ubuntu1~20.04) 9.3.0

Additional context
Add any other context about the problem here.

For circuit_model, type=ccff, currently, OpenFPGA only allow single data_in port. For testability purpose, we need a 2nd data_in port (ex, Test_data_in), similarly to most scan-able flipfiop.

Alternatively, we can create a wrapper on top of scan-able flipflop, with both data_in port and Test_data_in port shorted. Such that, "ccff" is still considered as a single data_in port by OpenFPGA.

Describe the bug
In auto-generated Verilog netlists, the clock ports defined in the top-level pb_type of VPR architecture file are not connected to the actual clock ports of registers/flip-flops.
This will lead to floating nets in physical design and potential DRC errors.

To Reproduce
Steps to reproduce the behavior:

1. Checkout github repo
2. Run an example test case
3. Check the Verilog netlist in lb/clb.v

Expected behavior
The clock ports defined in the top-level pb_type of VPR architecture file should be connected to the actual clock ports of registers/flip-flops.

Enviornment (please complete the following information):

• OS: CentOs
• Compiler: gcc-8.4
• Version: latest master

I try to use python3 to run openfpga flow, but there are some error which I can't fix:

lab601@lab601-VirtualBox:~/Desktop/OpenFPGA-master/openfpga_flow/scripts/test$ python3 ../run_fpga_flow.py k6_N10_sram_chain_HC_template.xml alu4.v
INFO - Validating commnad line arguments
INFO - Run directory : /home/lab601/Desktop/OpenFPGA-master/tmp
INFO - Running "yosys_vpr" Flow
INFO - Extracted lut_size size from arch XML = 6
INFO - Running Yosys with lut_size = 6
ERROR - Failed to run yosys
Traceback (most recent call last):
File "../run_fpga_flow.py", line 454, in run_yosys_with_abc
File "/usr/lib/python3.6/subprocess.py", line 438, in run
output=stdout, stderr=stderr)
subprocess.CalledProcessError: Command '['/home/lab601/Desktop/OpenFPGA-master/yosys/yosys', 'yosys.ys']' returned non-zero exit status 1.
ERROR - Current working directory : /home/lab601/Desktop/OpenFPGA-master/tmp
ERROR -
ERROR - Exiting . . . . . .

I don't know what's wrong about yosys. If anyone can express their idea, I would appreciate it !

Is your feature request related to a problem? Please describe.
During adder implementation, if yosys has to synthesise an adder as a hard-macro and then in OpenFPGA flow, this is implemented as LUT+carry_follower where LUT can be a combination of LUT4 with LUT2s or LUT3 with LUT2s. As yosys is implementing it as a hard-macro and it comes as a subckt in openfpga with INIT params that is an alternate to truth table that generally present in blif when luts are represented as .names.

Describe the solution you'd like
OpenFPGA should enable parsing parameters that has information similar to what a truth table provides to .names instances in blif

Describe alternatives you've considered
Alternate solution considered is to implement adder module in yosys in terms of LUT3+LUT2s+carry_follower. However, there is no guarantee in vpr that packers packs them all together so it may not provide a robust solution.

Additional context
Add any other context or screenshots about the feature request here.

Describe the bug
Currently, pre-processing flags that are auto-generated by OpenFPGA lack a clear organization.

• The Verilog netlist fpga_define.v includes pro-processing flags that are only used by testbenches and simulations.
• The Verilog netlist [define_simulation.v] should include the pro-processing flags that are only used by testbenches and simulations.

An example of content of fpga_defines.v

//-------------------------------------------
//	FPGA Synthesizable Verilog Netlist
//	Description: Preprocessing flags to enable/disable features in FPGA Verilog modules
//	Author: Xifan TANG
//	Organization: University of Utah
//	Date: Sat Nov 21 16:29:01 2020
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps

`define ENABLE_TIMING 1

`define ENABLE_SIGNAL_INITIALIZATION 1

`define ICARUS_SIMULATOR 1

In particular, the signal initialization codes are currently embedded in the Verilog modules. These codes are designed to help convergence of HDL simulators when dealing with combinational loops inside FPGA fabrics, which should be generated along with testbenches rather than hardware description.
The outcome is

• The auto-generated Verilog modules are not synthesizable. Users have to manually remove the signal initialization codes when porting the Verilog netlists to synthesis tools, e.g., Design Compiler.
• The signal initialization have to be manually added to testbenches for HDL simulations. This is not a trivial task, which demands a deep understanding on FPGA architecture. The codes should be auto-generated.

Expected behavior
In principle,

• the pre-processing flags for hardware description (which matters if a hardware resource is defined or not) should be placed in a Verilog netlist. The netlist should be generated when execute command write_fabric_verilog. These flags can be included when chip designers implement physical designs.
• the pre-processing flags for testbenches and simulations should be placed in a separated Verilog netlist than those pre-processing flags for hardware description. The netlist should be generated when execute command write_verilog_testbench
• Signal initialization should be removed from auto-generated Verilog modules. These codes should be generated in Verilog testbenches. A pre-processing flag can switch these codes on/off when running simulations.
• Icarus pre-processing flag should be moved to the netlist that contains simulation flags only.

Environment (please complete the following information):

• OS: CentOS, Ubuntu
• Compiler: gcc-8.4
• Version: latest master

It looks like OpenFPGA is already using Sphinx for it's documentation. There are a number of extensions that the SymbiFlow project and Antmicro have been working on to make Sphinx documentation for hardware look and work better!

• https://github.com/SymbiFlow/sphinx_symbiflow_theme -- A martial design based theme for Sphinx which we are using for our other hardware projects. I recommend picking a yellow or orange primary color for OpenFPGA (purple == symbiflow, green == skywater-pdk, light blue / cyan == fomu workshop).
• https://github.com/SymbiFlow/sphinxcontrib-hdl-diagrams -- Automatic generation of diagrams using Yosys + netlistsvg from Verilog. Good example is the https://github.com/SymbiFlow/python-symbiflow-v2x
• https://github.com/SymbiFlow/sphinx-verilog-domain -- Support for documenting verilog using sphinx (in a similar manner to how you can use Sphinx to document Python).
• https://github.com/SymbiFlow/sphinxcontrib-session -- Sphinx extension for making nice examples sessions.

I try to build OpenFPGA, and cmake has a error result, this is content of the CMakeError.log file:

Performing C++ SOURCE FILE Test CXX_COMPILER_SUPPORTS_-Wcast-allign failed with the following output:
Change Dir: /home/lab601/桌面/OpenFPGA-master/build/CMakeFiles/CMakeTmp

Run Build Command(s):/usr/bin/make cmTC_1ed51/fast
/usr/bin/make -f CMakeFiles/cmTC_1ed51.dir/build.make CMakeFiles/cmTC_1ed51.dir/build
make[1]: Entering directory '/home/lab601/桌面/OpenFPGA-master/build/CMakeFiles/CMakeTmp'
Building CXX object CMakeFiles/cmTC_1ed51.dir/src.cxx.o
/usr/bin/c++ -DCXX_COMPILER_SUPPORTS_-Wcast-allign -Wcast-allign -std=c++14 -o CMakeFiles/cmTC_1ed51.dir/src.cxx.o -c /home/lab601/桌面/OpenFPGA-master/build/CMakeFiles/CMakeTmp/src.cxx
c++: error: unrecognized command line option '-Wcast-allign'; did you mean '-Wcast-align'?
CMakeFiles/cmTC_1ed51.dir/build.make:65: recipe for target 'CMakeFiles/cmTC_1ed51.dir/src.cxx.o' failed
make[1]: *** [CMakeFiles/cmTC_1ed51.dir/src.cxx.o] Error 1
make[1]: Leaving directory '/home/lab601/桌面/OpenFPGA-master/build/CMakeFiles/CMakeTmp'
Makefile:121: recipe for target 'cmTC_1ed51/fast' failed
make: *** [cmTC_1ed51/fast] Error 2

Source file was:
int main() { return 0; }

is the command line '-Wcast-allign' wrong? Or maybe the version of the compiler isn't right?

While using the docker flow and running the ERI demo and after generating the bitstream there is a problem of finding some module definitions in the verifications phase.
stderr.txt
stdout.txt

Hello,

1- In global_ports.sdc, some global ports are defined as clocks while they clearly should not:

create_clock Reset[0]-period 10 -waveform {0 5} [list [get_ports { Reset[0]}]]
set_drive 0 Reset[0]

Assuming the reset is assynchronous, I would suggest:

set_false_path -from [get_ports { Reset[0]}]

2- I would suggest defining the clock following the "standard" syntax (as defined in the "Constraining Designs for Synthesis and Timing Analysis: A Practical Guide to Synopsys Design Constraints (SDC)" book for instance):
create_clock -name prog_clk[0] -period 100 -waveform {0 50} [get_ports {prog_clk[0]}]
Instead of
create_clock prog_clk[0]-period 100 -waveform {0 50}

Thanks,
Edouard

Problem

frontends/ast/dpicall.cc:25:10: fatal error: ffi.h: No such file or directory
   25 | #include <ffi.h>
      |          ^~~~~~~
compilation terminated.

Steps

git clone https://github.com/LNIS-Projects/OpenFPGA.git
cd OpenFPGA
mkdir build; cd build
cmake .. 
make  

Solution

I think your Cmake is missing a required package, at least for newer version of Ubuntu. I solved the issue with:

sudo apt-get install libffi-dev

Envionment

$ lsb_release -a

No LSB modules are available.
Distributor ID:	Ubuntu
Description:	Ubuntu 20.04.1 LTS
Release:	20.04
Codename:	focal

Hi,

this time i wrote a new custom block called "blackbox", which includes an adder and a flipflop module in the vpr-arch, and want to link it with the circuit model in the openfppa-arch. Unfortunately it shows me an error called "pb_type missing circuit binding". I checked pb_type annotation part with the tutorial and the examples you have given, but didn't find any problems.
Can you please give me some advice?

xml.zip

Is your feature request related to a problem? Please describe.
As OpenFPGA is a modularized codebase, unit tests can be easily built.
Currently, unit tests are available in the OpenFPGA library, for example, the architecture XML parser
It would be useful to keep tracking these libraries by running unit tests in CI.

Describe the solution you'd like

• Create a job in current flow to accommodate these unit tests.
• Add more unit tests for these libopenfpga libraries.

Is your feature request related to a problem? Please describe.
OpenFPGA has embraced the shell-like interface while the old command-line interface has been dropped.
There are many obsoleted codes in the run_fpga_flow.py which is designed for the command-line interface.
This has confused users many times

Describe the solution you'd like
Remove these dead codes in the Python scripts

Hi, can OpenFPGA build a bidir segment FPGA architecture?
I tried to change a undir segment FPGA, which was k6_N10_sram_chain_HC_template.xml, to a bidir segment by modifying the content of the <segmentlist> tag and the <switchlist> tag. This way was successful in VPR, but was failed in OpenFPGA. I tried to look for the example xml files of the bidir FPGA architectures, but I found no one. I also read the OpenFPGA documentation, but I couldn't find the content about describing a bidir FPGA architecture.

If there is no ".latch" in the blif but some other submodules using a clock, the tool doesn't understand it has to map the clock stimuli on the clock port of the fpga.

FuseSoC is the "apt-get" of HDL cores. It would be good if you could easily run a FuseSoC design through OpenFPGA and see how big your FPGA would need to be.

You would probably need to add OpenFPGA support into edalize first.

Describe the bug
https://openfpga.readthedocs.io/en/master/tutorials/tools.html etc are dead.

To Reproduce
click on any of the documentation links in the readme
Expected behavior
to link to the docs :)

In some modules (cby_1__1_ for instance), some ports are declared (clk[0], Reset[0]) but are never used by the module.
It would be great if those port were automatically removed (if unused) during the Verilog generation.

hey guys,
hiii
can you guys make a screencast/video series for the detailed usage of this tool..?
i know there is detailed documentation but still if we get a video series that would be really great..
sorry for my poor english..
cheers...

You might want to consider adopting the usage of the SymbiFlow Yosys Plugins @ https://github.com/SymbiFlow/yosys-symbiflow-plugins to improve your SDC support (and future timing driven synthesis). This works by importing the SDC into Yosys cells and then writing out a modified SDC at the end. This means if Yosys changes module names or optimizes out your modules you still end up with a valid SDC file you can pass to VPR.

Current ccff type has only one output port for the purposes of (1) building configuration chain, and (2) controlling on multiplexer. The drawback is, unwanted activities during programming configuration sequence.

By adding a 2nd output port, which can be gated by "configuration done". Such that, the new added output is to keep multiplexers quite during configuration programming, and the original output is to form configuration chain. The next step, is to be able to direct OpenFPGA, to connect the outputs for each of its purpose.

Alternatively, we can build a wrapper to create the 2nd output, which is gated by input, "configuration done". After HDL is generated, do post-process on netlist to correct the connections on the two output ports. (currently, the 2nd output port is not connected to anywhere.)

Describe the bug
Self-testing full testbench does not cover any configuration phase.
For example, if the configuration done signal 'config_done' is never raised.
The auto-check still passed.
This will cause true-negative checking in regression tests

Expected behavior
The error checker should capture if the configuration done signal is raised after a simulation period.
If not raised, error counter should be incremented.

Describe the bug
In the Github Action workflow, ccache is enabled to cache compilations results, so that CI runtime can be reduced.
Similar caching was done in the Travis CI script, which effectively reduces compilation runtime from 30 minutes to 5 minutes in most cases.
However, currently the ccache seems not behave as expected. Compilation time in Github Action workflows is around 30 minutes for each run.

To Reproduce
Steps to reproduce the behavior:

1. Run any workflow in the github action

Expected behavior
The compilation time for each workflow should be around 5 minutes when an incremental change is pushed.

Screenshots
If applicable, add screenshots to help explain your problem.

Enviornment (please complete the following information):

• OS: Ubuntu 18.04 from Github Action settings
• Compiler: gcc-8
• Version: latest master

1->I have successfully compiled the OpenFPGA project.
I want to access OpenFPGA Shell.
Do i need to setup environment variable to access this shell globally..?

Describe the bug
Need to tie global port, "clk" and "Reset" from tile "io" together with tile "clb"'s ports.
Example of openfpga XML codes below,
<tile_annotations>
<global_port name="clk" tile_port="clb.clk" is_clock="true" default_val="0"/>




<global_port name="Reset" tile_port="clb.reset" is_reset="true" default_val="1"/>




</tile_annotations>
To Reproduce
To reproduce,
(1)sample above example codes to openfpga XML.
(2)require a corresponding tile with either "clk" or "reset" port in vpr XML

Expected behavior
Expecting port, "clk" and "Reset" are globally tie together from each "io" tile (in addition to tile "clb").
Particularly, if tile "capacity" is greater than 1, also need to make sure, "clk" and "Reset" are also tied respectively.

Screenshots
If applicable, add screenshots to help explain your problem.

Enviornment (please complete the following information):

• OS: [e.g. CentOs, Ubuntu]
• Compiler [e.g. gcc, clang]
• Version [e.g. Github commit id]

Additional context
Add any other context about the problem here.

Tileable rr_graph failed in routing when

• a 1x1 array is used
• the routing channel width is set to a fixed number, i.e., 200 or 100 etc.

Architecture file that fails:
k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm

Benchmark tried:
2-input and gate

Error message:

Warning 37: No routing path for connection to sink_rr 180, retrying with full device bounding box
Cannot route from clb.O[19] (RR node: 83 type: SOURCE location: (1,1) class: 27 capacity: 1) to io[0].outpad[0] (RR node: 180 type: SINK location: (2,1) class: 12 capacity: 1) -- no possible path
Failed to route connection from 'c' to 'out:c' for net 'c' (#2)
Routing failed.

Is your feature request related to a problem? Please describe.
Travis-CI has changed its price model which gives us only a limited number of free CI runs once (1000 builds).
See https://blog.travis-ci.com/2020-11-02-travis-ci-new-billing
We cannot use Travis-CI freely as we already reached our limits.

Describe the solution you'd like
Move to Github Actions which gives us 3000 minutes free build per month (as we are already in Github team plan).

Describe alternatives you've considered
I am wondering if there is any CI platform we can try.

Is your feature request related to a problem? Please describe.
There have been several tape-out completed by using OpenFPGA. For example, the SOFA series. To keep a constant support on these tape-outs, OpenFPGA's regression tests should test bitstream generation and HDL simulation on existing netlists.

However, current regression tests only focus on a complete flow: netlist generation -> bitstream/testbench generation -> HDL simulation.
This may cause a tape-out to be disconnected from the OpenFPGA support:

• Any changes on netlist generator will cause a change on bitstream generator
• A complete flow is always working as the generators are geared well internally
• A tape-out has a harden netlist which may not work when netlist generator is upgraded.

Describe the solution you'd like
There is a strong to upgrade the OpenFPGA flow scripts to

• Take an existing netlist (could from post-PnR netlist)
• Generate bitstream and testbenches using the architecture description files (used to build the tape-out)
• Run HDL simulation to ensure functional correctness

It was requested by the University of Washington.

Pb: Most benchmarks or functional verilogs are actually projects with different files. Accepting multiple files would be a good step forward (also check if it is possible to use wild cards (*) or glob / similar function.

Comment: Need to check if it is possible to do under Yosys. This is going to be our limitations.