ERROR: [DRC UCIO-1] Unconstrained Logical Port: 42 out of 52 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: customout[2:0], io_dip[2], io_dip[1], io_dip[0], io_led[23:0], io_seg[7:0], and io_sel[3:0]. ERROR: [Vivado 12-13638] Failed runs(s) : 'impl_1'

Is it planned to support Vivado 2023.2?

I didn't check the repository in advance and installed 2023.2 on my system and when I run:

cd kv260/platforms/vivado/kv260_ispMipiRx_vcu_DP
make xsa

I got the following error:

ERROR: [IP_Flow 19-3476] Tcl error in create_gui procedure for BD Cell 'clk_wiz_audio'. expected floating-point number but got "Unable to get value from speedsfile for keyword MM"
ERROR: [IP_Flow 19-3428] Failed to create Customization object clk_wiz_audio
CRITICAL WARNING: [IP_Flow 19-5622] Failed to create IP instance 'kv260_ispMipiRx_vcu_DP_clk_wiz_audio_0'. Failed to customize IP instance 'kv260_ispMipiRx_vcu_DP_clk_wiz_audio_0'. Failed to load customization data
ERROR: [BD 41-1712] Create IP failed with errors
ERROR: [BD 5-7] Error: running create_bd_cell  -vlnv xilinx.com:ip:clk_wiz:6.0 -type ip -name clk_wiz_audio .
create_bd_cell: Time (s): cpu = 00:00:05 ; elapsed = 00:00:21 . Memory (MB): peak = 2500.379 ; gain = 931.531 ; free physical = 5007 ; free virtual = 41952
ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.

    while executing
"create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz clk_wiz_audio "
    (procedure "create_hier_cell_audio_ss_0" line 78)
    invoked from within
"create_hier_cell_audio_ss_0 [current_bd_instance .] audio_ss_0"
    (procedure "create_root_design" line 52)
    invoked from within
"create_root_design """
    (file "./scripts/config_bd.tcl" line 884)

    while executing
"source $bd_tcl_dir/config_bd.tcl"
    (file "scripts/main.tcl" line 47)
INFO: [Common 17-206] Exiting Vivado at Sun Dec 17 10:49:26 2023...

hello,my friends, recently I use kv260 to study as a student, and I got petalinux2023.2、vitis 2023.2 、vivado2023.2 installed. when I follow this tutorial https://xilinx.github.io/kria-apps-docs/kv260/2022.1/build/html/docs/build_accel.html, I got "make overlay OVERLAY=smartcam failed" error message，I am new to this, so please give me some advice about how to fix this. And I am confused with question of "why I cant find tutorial about 2023.2 versions". The detailed message is as belowed.

16:04:26] Starting bitstream generation..
[16:04:26] Phase 16 Post-Route Event Processing
[16:06:53] Run vpl: Step impl: Failed
[16:06:54] Run vpl: FINISHED. Run Status: impl ERROR

===>The following messages were generated while Compiling (bitstream) accelerator binary: dpu Log file: /home/why/prj/kria-vitis-platforms/kv260/overlays/examples/smartcam/binary_container_1/link/vivado/vpl/prj/prj.runs/impl_1/runme.log :
ERROR: [VPL 101-2] design did not meet timing - Design failed to meet timing.
Failed timing checks (paths):
{kv260_ispMipiRx_vcu_DP_i/DPUCZDX8G_1/inst/dpu_xrt_i/dpu_wrapper/m_dpu_top/m_buf_writer/dm_write_ctrl/cm_buf_wctrl_augm/state_machines[0].in_chs_cnt_reg[9]/C --> kv260_ispMipiRx_vcu_DP_i/DPUCZDX8G_1/inst/dpu_xrt_i/dpu_wrapper/m_dpu_top/m_buf_writer/dm_write_ctrl/cm_buf_wctrl_augm/state_machines[0].in_chs_cnt_reg[0]/CE}

Please check the routed checkpoint (dr_routed_timing.dcp) and timing summary report (dr_timing_summary.rpt) for more information.

ERROR: [VPL 101-3] sourcing script /home/why/prj/kria-vitis-platforms/kv260/overlays/examples/smartcam/binary_container_1/link/vivado/vpl/scripts/impl_1/_full_write_bitstream_pre.tcl failed

===>The following messages were generated while creating FPGA bitstream. Log file: /home/why/prj/kria-vitis-platforms/kv260/overlays/examples/smartcam/binary_container_1/link/vivado/vpl/runme.log :
ERROR: [VPL 12-13638] Failed runs(s) : 'impl_1'
ERROR: [VPL 60-773] In '/home/why/prj/kria-vitis-platforms/kv260/overlays/examples/smartcam/binary_container_1/link/vivado/vpl/vivado.log', caught Tcl error: ERROR: [Common 17-39] 'wait_on_runs' failed due to earlier errors.
WARNING: [VPL 60-732] Link warning: No monitor points found for BD automation.
ERROR: [VPL 60-704] Integration error, Failed to complete hardware generation. The run name is 'impl_1'. An error stack with function names and arguments may be available in the 'vivado.log'.
ERROR: [VPL 60-1328] Vpl run 'vpl' failed
ERROR: [VPL 60-806] Failed to finish platform linker
INFO: [v++ 60-1442] [16:06:54] Run run_link: Step vpl: Failed
Time (s): cpu = 00:00:42 ; elapsed = 01:54:35 . Memory (MB): peak = 468.906 ; gain = 0.000 ; free physical = 26651 ; free virtual = 120928
ERROR: [v++ 60-661] v++ link run 'run_link' failed
ERROR: [v++ 60-626] Kernel link failed to complete
ERROR: [v++ 60-703] Failed to finish linking
INFO: [v++ 60-1653] Closing dispatch client.
make[1]: *** [Makefile:75：binary_container_1/dpu.xclbin] 错误 1
make[1]: 离开目录“/home/why/prj/kria-vitis-platforms/kv260/overlays/examples/smartcam”
make: *** [Makefile:61：overlays/examples/smartcam/binary_container_1/link/int/system.bit] 错误 2

Hi,

I want to modify the overlay examples to fit my design. Is there any instruction about importing them into GUI?

I follow the tutorial here to build the application, but I don't know how to import them.
(https://xilinx.github.io/kria-apps-docs/main/build/html/docs/build_vitis_platform.html)

I ran this

make platform PLATFORM=kv260_ispMipiRx_rpiMipiRx_DP

what are the next steps to try this out on the kv260 board?

Please help me!
My System is Ubuntu 20.04.03(amd64)
The version of the Vitis is 2021.1. And I also source all of settings64.sh before I run;
root@Z370-AORUS-Gaming-7:/home/nvidia/prj_k26/kv260-vitis# source /opt/Xilinx_2021/Vivado/2021.1/settings64.sh
root@Z370-AORUS-Gaming-7:/home/nvidia/prj_k26/kv260-vitis# source /opt/Xilinx_2021/Vitis_HLS/2021.1/settings64.sh
root@Z370-AORUS-Gaming-7:/home/nvidia/prj_k26/kv260-vitis# source /opt/Xilinx_2021/Vitis/2021.1/settings64.sh
root@Z370-AORUS-Gaming-7:/home/nvidia/prj_k26/kv260-vitis# make platform PFM=kv260_ispMipiRx_vcu_DP

The error is:

****** Vivado v2021.1 (64-bit)
**** SW Build 3247384 on Thu Jun 10 19:36:07 MDT 2021
**** IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021
** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.

source run_ippack.tcl -notrace
ERROR: '2201251806' is an invalid argument. Please specify an integer value.
while executing
"rdi::set_property core_revision 2201251806 {component component_1}"
invoked from within
"set_property core_revision $Revision $core"
(file "run_ippack.tcl" line 1186)
INFO: [Common 17-206] Exiting Vivado at Tue Jan 25 18:06:44 2022...
ERROR: [IMPL 213-28] Failed to generate IP.
INFO: [HLS 200-111] Finished Command export_design CPU user time: 10.35 seconds. CPU system time: 0.53 seconds. Elapsed time: 12.13 seconds; current allocated memory: 473.184 MB.
command 'ap_source' returned error code
while executing
"source /home/nvidia/prj_k26/kv260-vitis/platforms/vivado/kv260_ispMipiRx_vcu_DP/project/kv260_ispMipiRx_vcu_DP.runs/kv260_ispMipiRx_vcu_DP_v_frmbuf_wr..."
("uplevel" body line 1)
invoked from within
"uplevel #0 [list source $arg] "

INFO: [HLS 200-112] Total CPU user time: 47.03 seconds. Total CPU system time: 2.11 seconds. Total elapsed time: 49.24 seconds; peak allocated memory: 470.467 MB.
INFO: [Common 17-206] Exiting vitis_hls at Tue Jan 25 18:06:47 2022...
ERROR: [Vivado 12-8300] Launch HLS failed! Please see vitis_hls.log for details.
INFO: [Common 17-206] Exiting Vivado at Tue Jan 25 18:06:47 2022...

Thanks in advance!

Win10 xilinx 2022.1, When I run 'make xsa' command I get the following error:

kria-vitis-platforms\kv260\platforms\vivado\kv260_vcuDecode_vmixDP>make xsa
/bin/vivado -mode batch -notrace -source scripts/main.tcl -tclargs -jobs 8
process_begin: CreateProcess(NULL, sh.exe -c "/bin/vivado -mode batch -notrace -source scripts/main.tcl -tclargs -jobs 8", ...) failed.
make (e=2): The system cannot find the file specified.
make: *** [Makefile:29: project/kv260_vcuDecode_vmixDP.xsa] Error 2

Hi,

how to build defect-detection app from source?

I used below source and revision.

- petalinux : xilinx-k26-starterkit-v2021.1-final.bsp
- vivado: 2020.2.2
- kv260-vitis: branch = release-2020.2.2_k26  (https://github.com/Xilinx/kv260-vitis）
- device-tree: branch = release-2020.2.2_k26 (https://github.com/Xilinx/device-tree-xlnx)

I also try below combintaion, both failed.

- petalinux : xilinx-k26-starterkit-v2021.1-final.bsp
- vivado: 2021.1
- kv260-vitis: branch = release-2021.1 (https://github.com/Xilinx/kv260-vitis）
- device-tree: branch = release-2021.1 (https://github.com/Xilinx/device-tree-xlnx)

I can build petalinux image with app, please reference this link Xilinx/kria-apps-firmware#2 (comment)
but i found the dmesg with error when use the New FPGA Firmware(app) I build.

[   41.405160] xilinx-csi2rxss 80030000.mipi_csi2_rx_subsystem: missing xlnx,csi-pxl-format property

I think this issue is caused by the .dtsi file - tool auto generated.

xlnx,csi-pxl-format = "YUV422_8bit"; => this setting cause the error in .dtsi file

• detail error information in this link Xilinx/kria-apps-firmware#2 (comment)

My question is - Can I use the DTG to generate the dtsi file from defect-detection PL design (.xsa file)? or I need to manual modify the dtsi file generated from DTG?

I used below command to auto generate .dtsi file, I reference this link https://xilinx.github.io/kria-apps-docs/creating_applications/1.0/build/html/docs/creating_applications_dtsi_dtbo_generation.html

xsct
hsi open_hw_design /home/tonyho/workspace/kv260-vitis/tony-firmware/save0307-2021.1/kv260_ispMipiRx_vmixDP_save0307-2021.1.xsa
hsi set_repo_path /home/tonyho/workspace/device-tree-xlnx
hsi create_sw_design device-tree -os device_tree -proc psu_cortexa53_0
hsi set_property CONFIG.dt_overlay true [hsi::get_os]
hsi generate_target -dir save0307-2021.1_xlnx_rel_v2021.1
hsi close_hw_design [hsi::current_hw_design]
exit

Note: the /home/tonyho/workspace/kv260-vitis/tony-firmware/save0307-2021.1/kv260_ispMipiRx_vmixDP_save0307-2021.1.xsa is the file i build from kv260-vitis and branch = release-2021.1

According to https://www.xilinx.com/downloadNav/embedded-design-tools/2020-2.html:

Please note that the 2020.2.2 release is only for device enablement of the Xilinx Kria SOM family. For all other devices and evaluation platforms, please use the standard 2020.2 release.

I fetched the 2020.2 release, installed and sourced it. Then, I followed the instructions provided in this repo's READMEs to build one (tried various, all fail) of the platforms:

source /tools/Xilinx/Vitis/2020.2/settings64.sh
git clone --recursive https://github.com/Xilinx/kv260-vitis.git
cd kv260-vitis/platforms 
make platform PLATFORM=kv260_ispMipiRx_vcu_DP
make -C vivado/kv260_ispMipiRx_vcu_DP xsa JOBS=8
make[1]: Entering directory '/home/xilinx/kv260-vitis/platforms/vivado/kv260_ispMipiRx_vcu_DP'
/tools/Xilinx/Vivado/2020.2/bin/vivado -mode batch -notrace -source scripts/main.tcl -tclargs -jobs 8

****** Vivado v2020.2 (64-bit)
  **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
  **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source scripts/main.tcl -notrace
WARNING: [Board 49-26] cannot add Board Part xilinx.com:k26c:part0:1.0 available at /home/xilinx/kv260-vitis/platforms/vivado/board_files/k26c/1.0/board.xml as part xck26-sfvc784-2lv-c specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:k26i:part0:1.0 available at /home/xilinx/kv260-vitis/platforms/vivado/board_files/k26i/1.0/board.xml as part xck26-sfvc784-2lvi-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kv260:part0:1.1 available at /home/xilinx/kv260-vitis/platforms/vivado/board_files/kv260/1.0/board.xml as part xck26-sfvc784-2lv-c specified in board_part file is either invalid or not available
WARNING: [Vivado 12-4842] No board parts matched 'get_board_parts *:kv260:* -latest_file_version'.
get_board_parts: Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 2363.254 ; gain = 0.023 ; free physical = 241 ; free virtual = 10453
WARNING: [Board 49-26] cannot add Board Part xilinx.com:k26c:part0:1.0 available at /home/xilinx/kv260-vitis/platforms/vivado/board_files/k26c/1.0/board.xml as part xck26-sfvc784-2lv-c specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:k26i:part0:1.0 available at /home/xilinx/kv260-vitis/platforms/vivado/board_files/k26i/1.0/board.xml as part xck26-sfvc784-2lvi-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kv260:part0:1.1 available at /home/xilinx/kv260-vitis/platforms/vivado/board_files/kv260/1.0/board.xml as part xck26-sfvc784-2lv-c specified in board_part file is either invalid or not available
WARNING: [Vivado 12-4842] No board parts matched 'get_board_parts {}'.
ERROR: [Common 17-55] 'get_property' expects at least one object.
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
INFO: [Common 17-206] Exiting Vivado at Fri Jun 11 15:53:23 2021...
make[1]: *** [Makefile:29: project/kv260_ispMipiRx_vcu_DP.xsa] Error 1
make[1]: Leaving directory '/home/xilinx/kv260-vitis/platforms/vivado/kv260_ispMipiRx_vcu_DP'
make: *** [Makefile:42: vivado/kv260_ispMipiRx_vcu_DP/project/kv260_ispMipiRx_vcu_DP.xsa] Error 2

I then attempted to do so bypassing the Makefile at this level and simply generating the xsa:

cd ~/kv260-vitis/platforms/vivado/kv260_ispMipiRx_DP
make xsa
/tools/Xilinx/Vivado/2020.2/bin/vivado -mode batch -notrace -source scripts/main.tcl

****** Vivado v2020.2 (64-bit)
  **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
  **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source scripts/main.tcl -notrace
WARNING: [Board 49-26] cannot add Board Part xilinx.com:k26c:part0:1.0 available at /home/xilinx/kv260-vitis/platforms/vivado/board_files/k26c/1.0/board.xml as part xck26-sfvc784-2lv-c specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:k26i:part0:1.0 available at /home/xilinx/kv260-vitis/platforms/vivado/board_files/k26i/1.0/board.xml as part xck26-sfvc784-2lvi-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kv260:part0:1.1 available at /home/xilinx/kv260-vitis/platforms/vivado/board_files/kv260/1.0/board.xml as part xck26-sfvc784-2lv-c specified in board_part file is either invalid or not available
WARNING: [Vivado 12-4842] No board parts matched 'get_board_parts *:kv260:* -latest_file_version'.
WARNING: [Board 49-26] cannot add Board Part xilinx.com:k26c:part0:1.0 available at /home/xilinx/kv260-vitis/platforms/vivado/board_files/k26c/1.0/board.xml as part xck26-sfvc784-2lv-c specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:k26i:part0:1.0 available at /home/xilinx/kv260-vitis/platforms/vivado/board_files/k26i/1.0/board.xml as part xck26-sfvc784-2lvi-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kv260:part0:1.1 available at /home/xilinx/kv260-vitis/platforms/vivado/board_files/kv260/1.0/board.xml as part xck26-sfvc784-2lv-c specified in board_part file is either invalid or not available
WARNING: [Vivado 12-4842] No board parts matched 'get_board_parts {}'.
ERROR: [Common 17-55] 'get_property' expects at least one object.
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
INFO: [Common 17-206] Exiting Vivado at Fri Jun 11 16:01:24 2021...
make: *** [Makefile:28: project/kv260_nlp.xsa] Error 1

Finally, the READMEs in the repo are insconsistent with https://xilinx.github.io/kria-apps-docs/master/docs/build_accel.html, which also fails to build in the manner described there.

Ping @chkohn, @sweatharao, @xlnx-yuxiz and @mohammedrafi-sk, It'd be great to get some help and address these issues.
Thanks!

I have built the kv260_ispMipiRx_vcu_DP platform provided in this repository and I am trying to synthesize the hello_world example from the Vitis Accel repository with this platform. However, the build fails with timing errors. This is my command line:

make sd_card TARGET=hw DEVICE=kv260_ispMipiRx_vcu_DP HOST_ARCH=aarch64 EDGE_COMMON_SW=/tools/xilinx/petalinux/2020.2/

And this is the end of the build log:

===>The following messages were generated while  Compiling (bitstream) accelerator binary: vadd Log file: /home/hamid/projects/Vitis_Accel_Examples/hello_world/_x.hw.kv260_ispMipiRx_vcu_DP/link/vivado/vpl/prj/prj.runs/impl_1/runme.log  :
ERROR: [VPL 101-2] design did not meet timing - Design failed to meet timing.
    Failed timing checks (paths):
        {kv260_ispMipiRx_vcu_DP_i/axi_ic_PS_0_S_AXI_HP1_FPD/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_data_inst/length_counter_1_reg[1]/C --> kv260_ispMipiRx_vcu_DP_i/axi_ic_PS_0_S_AXI_HP1_FPD/m00_couplers/m00_data_fifo/inst/gen_fifo.fifo_gen_inst/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_8SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram/ENARDEN}

    Please check the routed checkpoint (dr_routed_timing.dcp) and timing summary report (dr_timing_summary.rpt) for more information.
ERROR: [VPL 101-3] sourcing script /home/hamid/projects/Vitis_Accel_Examples/hello_world/_x.hw.kv260_ispMipiRx_vcu_DP/link/vivado/vpl/scripts/_full_write_bitstream_pre.tcl failed
ERROR: [VPL 60-773] In '/home/hamid/projects/Vitis_Accel_Examples/hello_world/_x.hw.kv260_ispMipiRx_vcu_DP/link/vivado/vpl/vivado.log', caught Tcl error:  problem implementing dynamic region, impl_1: write_bitstream ERROR, please look at the run log file '/home/hamid/projects/Vitis_Accel_Examples/hello_world/_x.hw.kv260_ispMipiRx_vcu_DP/link/vivado/vpl/prj/prj.runs/impl_1/runme.log' for more information
WARNING: [VPL 60-732] Link warning: No monitor points found for BD automation.
ERROR: [VPL 60-704] Integration error, problem implementing dynamic region, impl_1: write_bitstream ERROR, please look at the run log file '/home/hamid/projects/Vitis_Accel_Examples/hello_world/_x.hw.kv260_ispMipiRx_vcu_DP/link/vivado/vpl/prj/prj.runs/impl_1/runme.log' for more information
ERROR: [VPL 60-1328] Vpl run 'vpl' failed
ERROR: [VPL 60-806] Failed to finish platform linker
INFO: [v++ 60-1442] [16:37:14] Run run_link: Step vpl: Failed
Time (s): cpu = 00:00:09 ; elapsed = 00:17:51 . Memory (MB): peak = 1586.227 ; gain = 0.000 ; free physical = 147385 ; free virtual = 314962
ERROR: [v++ 60-661] v++ link run 'run_link' failed
ERROR: [v++ 60-626] Kernel link failed to complete
ERROR: [v++ 60-703] Failed to finish linking
INFO: [v++ 60-1653] Closing dispatch client.
Makefile:141: recipe for target 'build_dir.hw.kv260_ispMipiRx_vcu_DP/vadd.xclbin' failed
make: *** [build_dir.hw.kv260_ispMipiRx_vcu_DP/vadd.xclbin] Error 1

I have attached the timing summary, as well. Am I doing something wrong here?

dr_timing_summary.txt

Hi, I'm following instructions from the Xilinx docs for the KV260 Defect Detect application here, and can't get through the vivado flow, running the following command as per the doc page make xsa

Which then produces the following error:
ERROR: unexpected exception when evaluating tcl command
while executing
"generate_target all [get_files $proj_dir/${proj_name}.srcs/sources_1/bd/$proj_name/${proj_name}.bd]"
(file "scripts/main.tcl" line 60)

The same result occurs when attempting to create the XSA for the other applications and the error doesn't really provide any insight as to a root cause.

Pleas advise?

I have built the kv260_ispMipiRx_vcu_DP platform provided in this repository for use with the smartcam application on a KV260 starter kit.

My goal is to add VCU, MIPI, and DP support to my custom carrier card design and run the same smartcam application with the use of the PetaLinux drivers which I believe are at /dev/allegroIP (for VCU) and /dev/media0 (for MIPI). I want to be able to create and boot a PetaLinux project with those drivers loaded for this platform before I attempt to do it on my custom one.

So I created a Petalinux project from the kv260_ispMipiRx_vcu_DP.xsa file using --get-hw-description and the OS boots up properly but doesn't load the VCU or MIPI drivers. The default app that's loaded with xmutil is kv260-dp which doesn't load those drivers. When I load the kv260-smartcam app, all the drivers load properly. So I'm assuming the drivers are only loaded through accelerated apps using xmutil?

I generated a device tree overlay file from the kv260_ispMipiRx_vcu_DP.xsa by using the instructions here: Generate Device Tree Overlay

xsct

hsi open_hw_design <path to kv260_ispMipiRx_vcu_DP.xsa>
hsi set_repo_path <path to device-tree-xlnx repository>
hsi create_sw_design device-tree -os device_tree -proc psu_cortexa53_0
hsi set_property CONFIG.dt_overlay true [hsi::get_os]
hsi set_property CONFIG.dt_zocl true [hsi::get_os]
hsi generate_target -dir <desired_dts_filename>
hsi close_hw_design [hsi current_hw_design]

dtc -@ -O dtb -o pl.dtbo pl.dtsi

Then, I built an example vector add accelerated application using the KV260 Platform Tutorial and moved it to the accelerated app directory (/lib/firmware/xilinx) along with the DTBO device tree overlay file generated above. When I load it with xmutil, it loads the VCU drivers correctly to /dev/allegroIP but it doesn't load the MIPI drivers which I believe should be at /dev/media0.

Interestingly, I tried generating a DTBO file from the DTSI file found here and it loads all the drivers properly. This leads me to believe that there's something wrong with the DTSI file I generated myself. Can somebody help me figure out why my generated device tree file doesn't load the MIPI driver properly the way the kv260-smartcam.dtsi does? Thanks!

Here's my generated DTSI file can be found here.

Where can I find PetaLinux BSPs or configuration to build PetaLinux for platforms provided in this repository? At least I would expect a custom device-tree config to be provided for each platform.

I got errors in make overlay OVERLAY=smartcam. The error message in log file are follows,
grep -i2 error overlays/examples/smartcam/v++_pp_pipeline_accel_4240.backup.log
Then I got ...
===>The following messages were generated while performing high-level synthesis for kernel: pp_pipeline_accel Log file: /XXXX/kv260-vitis-release-2020.2.2_k26/overlays/examples/smartcam/_x/pp_pipeline_accel/pp_pipeline_accel/vitis_hls.log :
ERROR: [v++ 207-812] 'common/xf_common.hpp' file not found: /XXXX/kv260-vitis-release-2020.2.2_k26/overlays/examples/smartcam/xf_pp_pipeline_config.h:20:10
ERROR: [v++ 60-300] Failed to build kernel(ip) pp_pipeline_accel, see log for details: /XXXX/kv260-vitis-release-2020.2.2_k26/overlays/examples/smartcam/_x/pp_pipeline_accel/pp_pipeline_accel/vitis_hls.log
ERROR: [v++ 60-773] In '/XXXX/kv260-vitis-release-2020.2.2_k26/overlays/examples/smartcam/_x/pp_pipeline_accel/pp_pipeline_accel/vitis_hls.log', caught Tcl error: ERROR: [HLS 207-812] 'common/xf_common.hpp' file not found: /XXXX/kv260-vitis-release-2020.2.2_k26/overlays/examples/smartcam/xf_pp_pipeline_config.h:20:10
ERROR: [v++ 60-599] Kernel compilation failed to complete
ERROR: [v++ 60-592] Failed to finish compilation
INFO: [v++ 60-1653] Closing dispatch client.
where I can get this file?from include file, I will needs following files.
#include "common/xf_common.hpp"
#include "common/xf_utility.hpp"
#include "dnn/xf_preprocess.hpp"
#include "imgproc/xf_crop.hpp"
#include "imgproc/xf_cvt_color.hpp"
#include "imgproc/xf_cvt_color_1.hpp"
#include "imgproc/xf_duplicateimage.hpp"
#include "imgproc/xf_resize.hpp"
#include "xf_config_params.h"

I had read the issue in #1.
But I still fail to build in 2020.2.2 release.
my error log as below.
my system with 128G memory. I also change the JOBS from 8 to 1, but it still fail.
Does anything I missing? does I need to do something to avoid get_board_parts fail?
any comment is welcome.

xilinx@Ubuntu3:~/git2/kv260-vitis$ make overlay OVERLAY=smartcam
Create Vitis platform kv260_ispMipiRx_vcu_DP
make[1]: Entering directory '/home/xilinx/git/kv260-vitis/platforms'
make -C vivado/kv260_ispMipiRx_vcu_DP xsa JOBS=1
make[2]: Entering directory '/home/xilinx/git/kv260-vitis/platforms/vivado/kv260_ispMipiRx_vcu_DP'
/tools/Xilinx/Vivado/2020.2/bin/vivado -mode batch -notrace -source scripts/main.tcl -tclargs -jobs 1

****** Vivado v2020.2.2 (64-bit)
**** SW Build 3118627 on Tue Feb 9 05:13:49 MST 2021
**** IP Build 3115676 on Tue Feb 9 10:48:11 MST 2021
** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.

source scripts/main.tcl -notrace
WARNING: [Vivado 12-4842] No board parts matched 'get_board_parts :kv260: -latest_file_version'.
WARNING: [Vivado 12-4842] No board parts matched 'get_board_parts {}'.
ERROR: [Common 17-55] 'get_property' expects at least one object.
Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object.
INFO: [Common 17-206] Exiting Vivado at Wed Nov 10 21:51:59 2021...
make[2]: *** [Makefile:29: project/kv260_ispMipiRx_vcu_DP.xsa] Error 1
make[2]: Leaving directory '/home/xilinx/git/kv260-vitis/platforms/vivado/kv260_ispMipiRx_vcu_DP'
make[1]: *** [Makefile:42: vivado/kv260_ispMipiRx_vcu_DP/project/kv260_ispMipiRx_vcu_DP.xsa] Error 2
make[1]: Leaving directory '/home/xilinx/git/kv260-vitis/platforms'
make: *** [Makefile:78: /home/xilinx/git/kv260-vitis/platforms/xilinx_kv260_ispMipiRx_vcu_DP_202110_1/kv260_ispMipiRx_vcu_DP.xpfm] Error 2

The top-level Makefile does not seem to work on my environment:

$ make overlay OVERLAY=smartcam
/bin/sh: 3: [: smartcam: unexpected operator
/bin/sh: 3: [: aibox-reid: unexpected operator
/bin/sh: 3: [: defect-detect: unexpected operator
/bin/sh: 3: [: nlp-smartvision: unexpected operator
Invalid parameter OVERLAY=smartcam. Choose one of: smartcam aibox-reid defect-detect nlp-smartvision
Makefile:59: recipe for target 'overlays/examples/smartcam/binary_container_1/link/int/system.bit' failed
make: *** [overlays/examples/smartcam/binary_container_1/link/int/system.bit] Error 1

$ make platform PFM=kv260_vcuDecode_vmixDP
/bin/sh: 3: [: kv260_ispMipiRx_vcu_DP: unexpected operator
/bin/sh: 3: [: kv260_vcuDecode_vmixDP: unexpected operator
/bin/sh: 3: [: kv260_ispMipiRx_vmixDP: unexpected operator
/bin/sh: 3: [: kv260_ispMipiRx_DP: unexpected operator
Invalid parameter PFM=kv260_vcuDecode_vmixDP. Choose one of: kv260_ispMipiRx_vcu_DP kv260_vcuDecode_vmixDP kv260_ispMipiRx_vmixDP kv260_ispMipiRx_DP
Makefile:76: recipe for target '/home/hamid/projects/kv260-vitis/platforms/xilinx_kv260_vcuDecode_vmixDP_202022_1/kv260_vcuDecode_vmixDP.xpfm' failed
make: *** [/home/hamid/projects/kv260-vitis/platforms/xilinx_kv260_vcuDecode_vmixDP_202022_1/kv260_vcuDecode_vmixDP.xpfm] Error 1

The Makefile inside the "platform" folder seems to work fine, though.

Hi, I'm following instructions from the Xilinx doc, this page for the vitis flow and this one for vivado flow, but both are returning an error.

On vitis, the command "make platform PFM=kr260_tsn_rs485pmod" returns this error:
ERROR: [Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted:
kr260_tsn_rs485pmod_i/ta_dma_0/inst ()
kr260_tsn_rs485pmod_i/my_tsn_ip/inst/tsn_endpoint_block_0/inst/TSN_TOP ()

On vivado, the command "make xsa" returns this error:
make: *** No rule to make target '/data/ip/xilinx/axi_uartlite_v2_0', needed by 'ip/axi_uartlite_v2_0'. Stop.

Please advise?

Hello! I am trying to build the kv260_ispMipiRx_vcu_DP platform for Smartcam. I am using this manual for this (https://xilinx.github.io/kria-apps-docs/main/build/html/docs/smartcamera/smartcamera_landing.html#tutorials).
I also changed video input from the IAS to the Raspberry Pi connector.
But at the step "Integrating the overlay into the Platform" (https://xilinx.github.io/kria-apps-docs/main/build/html/docs/build_accel.html) the program displays an error message about failed timing one of HLS-core.

What do I need to do to fix it?
runme.log
terminal.txt

HI all,

I have request a evaluation license for TSN IP core and enable the license with vivado license manager.

But it still comes out following issue while I trying to build the platfrom.

make platform PFM=kr260_tsn_rs485pmod JOBS=4

Any idea about this issue?

Thanks,
JH